Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Microsemi Ocelot network Switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) ===============================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) The Microsemi Ocelot network switch can be found on Microsemi SoCs (VSC7513,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) VSC7514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: Should be "mscc,vsc7514-switch"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: Must contain an (offset, length) pair of the register set for each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   entry in reg-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   - "sys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - "rew"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - "qs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - "ptp" (optional due to backward compatibility)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   - "qsys"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   - "ana"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - "portX" with X from 0 to the number of last port index available on that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - interrupts: Should contain the switch interrupts for frame extraction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   frame injection and PTP ready.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - interrupt-names: should contain the interrupt names: "xtr", "inj". Can contain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   "ptp_rdy" which is optional due to backward compatibility.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - ethernet-ports: A container for child nodes representing switch ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) The ethernet-ports container has the following properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - #address-cells: Must be 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - #size-cells: Must be 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Each port node must have the following mandatory properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - reg: Describes the port address in the switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Port nodes may also contain the following optional standardised
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) properties, described in binding documents:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - phy-handle: Phandle to a PHY on an MDIO bus. See
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)   Documentation/devicetree/bindings/net/ethernet.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	switch@1010000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		compatible = "mscc,vsc7514-switch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		reg = <0x1010000 0x10000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		      <0x1030000 0x10000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		      <0x1080000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		      <0x10e0000 0x10000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		      <0x11e0000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		      <0x11f0000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		      <0x1200000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		      <0x1210000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		      <0x1220000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		      <0x1230000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		      <0x1240000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		      <0x1250000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		      <0x1260000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		      <0x1270000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		      <0x1280000 0x100>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		      <0x1800000 0x80000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		      <0x1880000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		reg-names = "sys", "rew", "qs", "ptp", "port0", "port1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			    "port2", "port3", "port4", "port5", "port6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 			    "port7", "port8", "port9", "port10", "qsys",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 			    "ana";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		interrupts = <18 21 22>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		interrupt-names = "ptp_rdy", "xtr", "inj";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		ethernet-ports {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 			port0: port@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 				reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 				phy-handle = <&phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 			port1: port@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 				reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 				phy-handle = <&phy1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) 	};