Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Microsemi MII Management Controller (MIIM) / MDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) =================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible: must be "mscc,ocelot-miim"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg: The base address of the MDIO bus controller register bank. Optionally, a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)   second register bank can be defined if there is an associated reset register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)   for internal PHYs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - #address-cells: Must be <1>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #size-cells: Must be <0>.  MDIO addresses have no size component.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupts: interrupt specifier (refer to the interrupt binding)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Typically an MDIO bus might have several children.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	mdio@107009c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 		compatible = "mscc,ocelot-miim";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		reg = <0x107009c 0x36>, <0x10700f0 0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		interrupts = <14>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		phy0: ethernet-phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	};