^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MediaTek Frame Engine Ethernet controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) =========================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) have dual GMAC each represented by a child node..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Ethernet controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible: Should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "mediatek,mt2701-eth": for MT2701 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "mediatek,mt7623-eth", "mediatek,mt2701-eth": for MT7623 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "mediatek,mt7622-eth": for MT7622 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "mediatek,mt7629-eth": for MT7629 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "ralink,rt5350-eth": for Ralink Rt5350F and MT7628/88 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - reg: Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - interrupts: Should contain the three frame engines interrupts in numeric
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) order. These are fe_int0, fe_int1 and fe_int2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clocks: the clock used by the core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - clock-names: the names of the clock listed in the clocks property. These are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "ethif", "esw", "gp2", "gp1" : For MT2701 and MT7623 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "ethif", "esw", "gp0", "gp1", "gp2", "sgmii_tx250m", "sgmii_rx250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck", "eth2pll" : For MT7622 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "ethif", "sgmiitop", "esw", "gp0", "gp1", "gp2", "fe", "sgmii_tx250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "sgmii_rx250m", "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii2_tx250m",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "sgmii2_rx250m", "sgmii2_cdr_ref", "sgmii2_cdr_fb", "sgmii_ck",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "eth2pll" : For MT7629 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - power-domains: phandle to the power domain that the ethernet is part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - resets: Should contain phandles to the ethsys reset signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - reset-names: Should contain the names of reset signal listed in the resets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) property
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) These are "fe", "gmac" and "ppe"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - mediatek,ethsys: phandle to the syscon node that handles the port setup
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - mediatek,infracfg: phandle to the syscon node that handles the path from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) GMAC to PHY variants, which is required for MT7629 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - mediatek,sgmiisys: a list of phandles to the syscon node that handles the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) SGMII setup which is required for those SoCs equipped with SGMII such
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) as MT7622 and MT7629 SoC. And MT7622 have only one set of SGMII shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) by GMAC1 and GMAC2; MT7629 have two independent sets of SGMII directed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) to GMAC1 and GMAC2, respectively.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - mediatek,pctl: phandle to the syscon node that handles the ports slew rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) and driver current: only for MT2701 and MT7623 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * Ethernet MAC node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - compatible: Should be "mediatek,eth-mac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - reg: The number of the MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - phy-handle: see ethernet.txt file in the same directory and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) the phy-mode "trgmii" required being provided when reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) is equal to 0 and the MAC uses fixed-link to connect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) with internal switch such as MT7530.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) eth: ethernet@1b100000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) compatible = "mediatek,mt7623-eth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg = <0 0x1b100000 0 0x20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) clocks = <&topckgen CLK_TOP_ETHIF_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) <ðsys CLK_ETHSYS_ESW>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) <ðsys CLK_ETHSYS_GP2>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) <ðsys CLK_ETHSYS_GP1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clock-names = "ethif", "esw", "gp2", "gp1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) interrupts = <GIC_SPI 200 IRQ_TYPE_LEVEL_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) GIC_SPI 199 IRQ_TYPE_LEVEL_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) GIC_SPI 198 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) power-domains = <&scpsys MT2701_POWER_DOMAIN_ETH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) resets = <ðsys MT2701_ETHSYS_ETH_RST>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) reset-names = "eth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) mediatek,ethsys = <ðsys>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mediatek,pctl = <&syscfg_pctl_a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) gmac1: mac@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) compatible = "mediatek,eth-mac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) phy-handle = <&phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) gmac2: mac@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) compatible = "mediatek,eth-mac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) phy-handle = <&phy1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mdio-bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) phy0: ethernet-phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) phy-mode = "rgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) phy1: ethernet-phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) phy-mode = "rgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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