^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MediaTek DWMAC glue layer controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This file documents platform glue layer for stmmac.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Please see stmmac.txt for the other unchanged properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) The device node has following properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - compatible: Should be "mediatek,mt2712-gmac" for MT2712 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg: Address and length of the register set for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupts: Should contain the MAC interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupt-names: Should contain a list of interrupt names corresponding to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) the interrupts in the interrupts property, if available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Should be "macirq" for the main MAC IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: Must contain a phandle for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clock-names: The name of the clock listed in the clocks property. These are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "axi", "apb", "mac_main", "ptp_ref", "rmii_internal" for MT2712 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - mac-address: See ethernet.txt in the same directory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - phy-mode: See ethernet.txt in the same directory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - mediatek,pericfg: A phandle to the syscon node that control ethernet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) interface and timing delay.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - mediatek,tx-delay-ps: TX clock delay macro value. Default is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) It should be defined for RGMII/MII interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) It should be defined for RMII interface when the reference clock is from MT2712 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - mediatek,rx-delay-ps: RX clock delay macro value. Default is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) It should be defined for RGMII/MII interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) It should be defined for RMII interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Both delay properties need to be a multiple of 170 for RGMII interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) or will round down. Range 0~31*170.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Both delay properties need to be a multiple of 550 for MII/RMII interface,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) or will round down. Range 0~31*550.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - mediatek,rmii-rxc: boolean property, if present indicates that the RMII
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) reference clock, which is from external PHYs, is connected to RXC pin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) on MT2712 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Otherwise, is connected to TXC pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - mediatek,rmii-clk-from-mac: boolean property, if present indicates that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) MT2712 SoC provides the RMII reference clock, which outputs to TXC pin only.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - mediatek,txc-inverse: boolean property, if present indicates that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 1. tx clock will be inversed in MII/RGMII case,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 2. tx clock inside MAC will be inversed relative to reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) which is from external PHYs in RMII case, and it rarely happen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 3. the reference clock, which outputs to TXC pin will be inversed in RMII case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) when the reference clock is from MT2712 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - mediatek,rxc-inverse: boolean property, if present indicates that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 1. rx clock will be inversed in MII/RGMII case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 2. reference clock will be inversed when arrived at MAC in RMII case, when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) the reference clock is from external PHYs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 3. the inside clock, which be sent to MAC, will be inversed in RMII case when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) the reference clock is from MT2712 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - assigned-clocks: mac_main and ptp_ref clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - assigned-clock-parents: parent clocks of the assigned clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) eth: ethernet@1101c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) compatible = "mediatek,mt2712-gmac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) reg = <0 0x1101c000 0 0x1300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) interrupt-names = "macirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) phy-mode ="rgmii-rxid";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) mac-address = [00 55 7b b5 7d f7];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) clock-names = "axi",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "apb",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "mac_main",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "ptp_ref",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "rmii_internal";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) clocks = <&pericfg CLK_PERI_GMAC>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) <&pericfg CLK_PERI_GMAC_PCLK>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) <&topckgen CLK_TOP_ETHER_125M_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) <&topckgen CLK_TOP_ETHER_50M_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) assigned-clocks = <&topckgen CLK_TOP_ETHER_125M_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) <&topckgen CLK_TOP_ETHER_50M_SEL>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) <&topckgen CLK_TOP_ETHER_50M_RMII_SEL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) assigned-clock-parents = <&topckgen CLK_TOP_ETHERPLL_125M>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) <&topckgen CLK_TOP_APLL1_D3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) <&topckgen CLK_TOP_ETHERPLL_50M>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) power-domains = <&scpsys MT2712_POWER_DOMAIN_AUDIO>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) mediatek,pericfg = <&pericfg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) mediatek,tx-delay-ps = <1530>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) mediatek,rx-delay-ps = <1530>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) mediatek,rmii-rxc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mediatek,txc-inverse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mediatek,rxc-inverse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) snps,txpbl = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) snps,rxpbl = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) snps,reset-gpio = <&pio 87 GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) snps,reset-active-low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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