^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Common MDIO bus multiplexer/switch properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) An MDIO bus multiplexer/switch will have several child busses that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) numbered uniquely in a device dependent manner. The nodes for an MDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) bus multiplexer/switch will have one child node for each child bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - mdio-parent-bus : phandle to the parent MDIO bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - Other properties specific to the multiplexer/switch hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Required properties for child nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg : The sub-bus number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Example :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* The parent MDIO bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) smi1: mdio@1180000001900 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) compatible = "cavium,octeon-3860-mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) reg = <0x11800 0x00001900 0x0 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) pair of GPIO lines. Child busses 2 and 3 populated with 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PHYs each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) mdio-mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) compatible = "mdio-mux-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) gpios = <&gpio1 3 0>, <&gpio1 4 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) mdio-parent-bus = <&smi1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mdio@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) phy11: ethernet-phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) interrupts = <10 8>; /* Pin 10, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) phy12: ethernet-phy@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) interrupts = <10 8>; /* Pin 10, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) phy13: ethernet-phy@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) interrupts = <10 8>; /* Pin 10, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) phy14: ethernet-phy@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) interrupts = <10 8>; /* Pin 10, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) mdio@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) phy21: ethernet-phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) interrupts = <12 8>; /* Pin 12, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) phy22: ethernet-phy@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) interrupts = <12 8>; /* Pin 12, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) phy23: ethernet-phy@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) interrupts = <12 8>; /* Pin 12, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) phy24: ethernet-phy@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) interrupts = <12 8>; /* Pin 12, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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