Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Properties for an MDIO bus multiplexer consumer device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This is a special case of MDIO mux  when MDIO mux is defined as a consumer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) of a mux producer device. The mux producer can be of any type like mmio mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) producer, gpio mux producer or generic register based mux producer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties in addition to the MDIO Bus multiplexer properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - compatible : should be "mmio-mux-multiplexer"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - mux-controls : mux controller node to use for operating the mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - mdio-parent-bus : phandle to the parent MDIO bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) each child node of mdio bus multiplexer consumer device represent a mdio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) for more information please refer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Documentation/devicetree/bindings/mux/mux-controller.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) and Documentation/devicetree/bindings/net/mdio-mux.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) In below example the Mux producer and consumer are separate nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) &i2c0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	fpga@66 { // fpga connected to i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 			     "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		reg = <0x66>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		mux: mux-controller { // Mux Producer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 			compatible = "reg-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 			#mux-control-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 					<0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) mdio-mux-1 { // Mux consumer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	compatible = "mdio-mux-multiplexer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	mux-controls = <&mux 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	mdio-parent-bus = <&emdio1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	mdio@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	mdio@8 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		reg = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 	..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mdio-mux-2 { // Mux consumer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 	compatible = "mdio-mux-multiplexer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 	mux-controls = <&mux 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	mdio-parent-bus = <&emdio2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 	mdio@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) 	mdio@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) 		reg = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) 	..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 	..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) };