Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Properties for the MDIO bus multiplexer/glue of Amlogic G12a SoC family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This is a special case of a MDIO bus multiplexer. It allows to choose between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) the internal mdio bus leading to the embedded 10/100 PHY or the external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) MDIO bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties in addition to the generic multiplexer properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible : amlogic,g12a-mdio-mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg: physical address and length of the multiplexer/glue registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clocks: list of clock phandle, one for each entry clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clock-names: should contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   * "pclk"   : peripheral clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   * "clkin0" : platform crytal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   * "clkin1" : SoC 50MHz MPLL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) mdio_mux: mdio-multiplexer@4c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	compatible = "amlogic,g12a-mdio-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	reg = <0x0 0x4c000 0x0 0xa4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	clocks = <&clkc CLKID_ETH_PHY>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		 <&xtal>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		 <&clkc CLKID_MPLL_5OM>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	clock-names = "pclk", "clkin0", "clkin1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	mdio-parent-bus = <&mdio0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	ext_mdio: mdio@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	int_mdio: mdio@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		internal_ephy: ethernet-phy@8 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			compatible = "ethernet-phy-id0180.3301",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 				     "ethernet-phy-ieee802.3-c22";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			reg = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			max-speed = <100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };