^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Properties for an MDIO bus multiplexer/switch controlled by GPIO pins.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This is a special case of a MDIO bus multiplexer. One or more GPIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) lines are used to control which child bus is connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties in addition to the generic multiplexer properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible : mdio-mux-gpio.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - gpios : GPIO specifiers for each GPIO line. One or more must be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Example :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) /* The parent MDIO bus. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) smi1: mdio@1180000001900 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) compatible = "cavium,octeon-3860-mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg = <0x11800 0x00001900 0x0 0x40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) An NXP sn74cbtlv3253 dual 1-of-4 switch controlled by a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) pair of GPIO lines. Child busses 2 and 3 populated with 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) PHYs each.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) mdio-mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) compatible = "mdio-mux-gpio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) gpios = <&gpio1 3 0>, <&gpio1 4 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) mdio-parent-bus = <&smi1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) mdio@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) phy11: ethernet-phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) interrupts = <10 8>; /* Pin 10, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) phy12: ethernet-phy@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) interrupts = <10 8>; /* Pin 10, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) phy13: ethernet-phy@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) interrupts = <10 8>; /* Pin 10, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) phy14: ethernet-phy@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) interrupts = <10 8>; /* Pin 10, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mdio@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) phy21: ethernet-phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) interrupts = <12 8>; /* Pin 12, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) phy22: ethernet-phy@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) interrupts = <12 8>; /* Pin 12, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) phy23: ethernet-phy@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) interrupts = <12 8>; /* Pin 12, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) phy24: ethernet-phy@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) marvell,reg-init = <3 0x10 0 0x5777>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) <3 0x11 0 0x00aa>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) <3 0x12 0 0x4105>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) <3 0x13 0 0x0a60>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) interrupt-parent = <&gpio>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) interrupts = <12 8>; /* Pin 12, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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