Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Marvell PXA168 Ethernet Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: should be "marvell,pxa168-eth".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: address and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: interrupt for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - clocks: pointer to the clock for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - port-id: Ethernet port number. Should be '0','1' or '2'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - #address-cells: must be 1 when using sub-nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #size-cells: must be 0 when using sub-nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - phy-handle: see ethernet.txt file in the same directory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The MAC address will be determined using the optional properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) defined in ethernet.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Sub-nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Each PHY can be represented as a sub-node. This is not mandatory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Sub-nodes required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - reg: the MDIO address of the PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	eth0: ethernet@f7b90000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		compatible = "marvell,pxa168-eth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		reg = <0xf7b90000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		clocks = <&chip CLKID_GETH0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		phy-handle = <&ethphy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		ethphy0: ethernet-phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	};