Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * IPQ806x DWMAC Ethernet controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The device inherits all the properties of the dwmac/stmmac devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) described in the file net/stmmac.txt with the following changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible: should be "qcom,ipq806x-gmac" along with "snps,dwmac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	      and any applicable more detailed version number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	      described in net/stmmac.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - qcom,nss-common: should contain a phandle to a syscon device mapping the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 		   nss-common registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - qcom,qsgmii-csr: should contain a phandle to a syscon device mapping the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 		   qsgmii-csr registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	gmac: ethernet@37000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		device_type = "network";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		compatible = "qcom,ipq806x-gmac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		reg = <0x37000000 0x200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		interrupts = <GIC_SPI 220 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		interrupt-names = "macirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		qcom,nss-common = <&nss_common>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		qcom,qsgmii-csr = <&qsgmii_csr>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		clocks = <&gcc GMAC_CORE1_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		clock-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		resets = <&gcc GMAC_CORE1_RESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		reset-names = "stmmaceth";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	};