Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) IMX8 glue layer controller, NXP imx8 families support Synopsys MAC 5.10a IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This file documents platform glue layer for IMX.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Please see stmmac.txt for the other unchanged properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) The device node has following properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - compatible:  Should be "nxp,imx8mp-dwmac-eqos" to select glue layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	       and "snps,dwmac-5.10a" to select IP version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks: Must contain a phandle for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clock-names: Should be "stmmaceth" for the host clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	       Should be "pclk" for the MAC apb clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	       Should be "ptp_ref" for the MAC timer clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	       Should be "tx" for the MAC RGMII TX clock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	       Should be "mem" for EQOS MEM clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 		- "mem" clock is required for imx8dxl platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 		- "mem" clock is not required for imx8mp platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - interrupt-names: Should contain a list of interrupt names corresponding to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		   the interrupts in the interrupts property, if available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 		   Should be "macirq" for the main MAC IRQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 		   Should be "eth_wake_irq" for the IT which wake up system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - intf_mode: Should be phandle/offset pair. The phandle to the syscon node which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	     encompases the GPR register, and the offset of the GPR register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		- required for imx8mp platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		- is optional for imx8dxl platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - intf_mode: is optional for imx8dxl platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - snps,rmii_refclk_ext: to select RMII reference clock from external.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	eqos: ethernet@30bf0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		compatible = "nxp,imx8mp-dwmac-eqos", "snps,dwmac-5.10a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		reg = <0x30bf0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			     <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		interrupt-names = "eth_wake_irq", "macirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		clocks = <&clk IMX8MP_CLK_ENET_QOS_ROOT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 			 <&clk IMX8MP_CLK_QOS_ENET_ROOT>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			 <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			 <&clk IMX8MP_CLK_ENET_QOS>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		clock-names = "stmmaceth", "pclk", "ptp_ref", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		assigned-clocks = <&clk IMX8MP_CLK_ENET_AXI>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 				  <&clk IMX8MP_CLK_ENET_QOS_TIMER>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 				  <&clk IMX8MP_CLK_ENET_QOS>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_266M>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 					 <&clk IMX8MP_SYS_PLL2_100M>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 					 <&clk IMX8MP_SYS_PLL2_125M>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		assigned-clock-rates = <0>, <100000000>, <125000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		nvmem-cells = <&eth_mac0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		nvmem-cell-names = "mac-address";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		nvmem_macaddr_swap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		intf_mode = <&gpr 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		status = "disabled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	};