^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Hisilicon MDIO bus controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: can be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) "hisilicon,hns-mdio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) "hisilicon,mdio"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) "hisilicon,hns-mdio" is recommended to be used for hip05 and later SOCs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) while "hisilicon,mdio" is optional for backwards compatibility only on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) hip04 Soc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - reg: The base address of the MDIO bus controller register bank.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - #address-cells: Must be <1>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #size-cells: Must be <0>. MDIO addresses have no size component.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Typically an MDIO bus might have several children.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) mdio@803c0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) compatible = "hisilicon,hns-mdio","hisilicon,mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) reg = <0x0 0x803c0000 0x0 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) ethernet-phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) ...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };