Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Hisilicon hix5hd2 gmac controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: should contain one of the following SoC strings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	* "hisilicon,hix5hd2-gmac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	* "hisilicon,hi3798cv200-gmac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	* "hisilicon,hi3516a-gmac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	and one of the following version string:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	* "hisilicon,hisi-gmac-v1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	* "hisilicon,hisi-gmac-v2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   The version v1 includes SoCs hix5hd2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   The version v2 includes SoCs hi3798cv200, hi3516a.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg: specifies base physical address(s) and size of the device registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   The first region is the MAC register base and size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   The second region is external interface control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupts: should contain the MAC interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - #address-cells: must be <1>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - #size-cells: must be <0>.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - phy-mode: see ethernet.txt [1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - phy-handle: see ethernet.txt [1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - clocks: clock phandle and specifier pair.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - clock-names: contain the clock name "mac_core"(required) and "mac_ifc"(optional).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - resets: should contain the phandle to the MAC core reset signal(optional),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 	the MAC interface reset signal(optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 	and the PHY reset signal(optional).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - reset-names: contain the reset signal name "mac_core"(optional),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	"mac_ifc"(optional) and "phy"(optional).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	The 1st cell is reset pre-delay in micro seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	The 2nd cell is reset pulse in micro seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	The 3rd cell is reset post-delay in micro seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) The MAC address will be determined using the properties defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) ethernet.txt[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - PHY subnode: inherits from phy binding [2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [1] Documentation/devicetree/bindings/net/ethernet.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) [2] Documentation/devicetree/bindings/net/phy.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	gmac0: ethernet@f9840000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		reg = <0xf9840000 0x1000>,<0xf984300c 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		interrupts = <0 71 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		phy-mode = "rgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		phy-handle = <&phy2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		mac-address = [00 00 00 00 00 00];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		clocks = <&crg HISTB_ETH0_MAC_CLK>, <&crg HISTB_ETH0_MACIF_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		clock-names = "mac_core", "mac_ifc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		resets = <&crg 0xcc 8>, <&crg 0xcc 10>, <&crg 0xcc 12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		reset-names = "mac_core", "mac_ifc", "phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		hisilicon,phy-reset-delays-us = <10000 10000 30000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		phy2: ethernet-phy@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	};