^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Hisilicon hip04 Ethernet Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Ethernet controller node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - compatible: should be "hisilicon,hip04-mac".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - reg: address and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - interrupts: interrupt for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - port-handle: <phandle port channel>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) phandle, specifies a reference to the syscon ppe node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) port, port number connected to the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) channel, recv channel start from channel * number (RX_DESC_NUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) group, field in the pkg desc, in general, it is the same as the port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - phy-mode: see ethernet.txt [1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - phy-handle: see ethernet.txt [1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) [1] Documentation/devicetree/bindings/net/ethernet.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * Ethernet ppe node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Control rx & tx fifos of all ethernet controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Have 2048 recv channels shared by all ethernet controllers, only if no overlap.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Each controller's recv channel start from channel * number (RX_DESC_NUM).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - compatible: "hisilicon,hip04-ppe", "syscon".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - reg: address and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * MDIO bus node:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - compatible: should be "hisilicon,mdio".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - Inherits from MDIO bus node binding [2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) [2] Documentation/devicetree/bindings/net/phy.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) mdio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) compatible = "hisilicon,mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) reg = <0x28f1000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) phy0: ethernet-phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) compatible = "ethernet-phy-ieee802.3-c22";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) marvell,reg-init = <18 0x14 0 0x8001>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) phy1: ethernet-phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) compatible = "ethernet-phy-ieee802.3-c22";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) marvell,reg-init = <18 0x14 0 0x8001>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ppe: ppe@28c0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) compatible = "hisilicon,hip04-ppe", "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) reg = <0x28c0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) fe: ethernet@28b0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) compatible = "hisilicon,hip04-mac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) reg = <0x28b0000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) interrupts = <0 413 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) phy-mode = "mii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) port-handle = <&ppe 31 0 31>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) ge0: ethernet@2800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) compatible = "hisilicon,hip04-mac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg = <0x2800000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) interrupts = <0 402 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) phy-mode = "sgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) port-handle = <&ppe 0 1 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) phy-handle = <&phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ge8: ethernet@2880000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) compatible = "hisilicon,hip04-mac";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) reg = <0x2880000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) interrupts = <0 410 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) phy-mode = "sgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) port-handle = <&ppe 8 2 8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) phy-handle = <&phy1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };