Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Hisilicon Fast Ethernet MAC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: should contain one of the following version strings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	* "hisilicon,hisi-femac-v1"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	* "hisilicon,hisi-femac-v2"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	and the soc string "hisilicon,hi3516cv300-femac".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg: specifies base physical address(s) and size of the device registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   The first region is the MAC core register base and size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   The second region is the global MAC control register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupts: should contain the MAC interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - clocks: A phandle to the MAC main clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - resets: should contain the phandle to the MAC reset signal(required) and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	the PHY reset signal(optional).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - reset-names: should contain the reset signal name "mac"(required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	and "phy"(optional).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - phy-mode: see ethernet.txt [1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - phy-handle: see ethernet.txt [1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - hisilicon,phy-reset-delays-us: triplet of delays if PHY reset signal given.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	The 1st cell is reset pre-delay in micro seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	The 2nd cell is reset pulse in micro seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	The 3rd cell is reset post-delay in micro seconds.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) The MAC address will be determined using the optional properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) defined in ethernet.txt[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) [1] Documentation/devicetree/bindings/net/ethernet.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	hisi_femac: ethernet@10090000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		compatible = "hisilicon,hi3516cv300-femac","hisilicon,hisi-femac-v2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		reg = <0x10090000 0x1000>,<0x10091300 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		interrupts = <12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		clocks = <&crg HI3518EV200_ETH_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		resets = <&crg 0xec 0>,<&crg 0xec 3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		reset-names = "mac","phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		mac-address = [00 00 00 00 00 00];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		phy-mode = "mii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		phy-handle = <&phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		hisilicon,phy-reset-delays-us = <10000 20000 20000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	};