Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Hisilicon Fast Ethernet MDIO Controller interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: should be "hisilicon,hisi-femac-mdio".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: address and length of the register set for the device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - clocks: A phandle to the reference clock for this device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - PHY subnode: inherits from phy binding [1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) [1] Documentation/devicetree/bindings/net/phy.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) mdio: mdio@10091100 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	compatible = "hisilicon,hisi-femac-mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	reg = <0x10091100 0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	clocks = <&crg HI3516CV300_MDIO_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	phy0: phy@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 		reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };