^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) =============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Freescale Frame Manager Device Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) CONTENTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - FMan Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - FMan Port Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - FMan MURAM Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - FMan dTSEC/XGEC/mEMAC Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - FMan IEEE 1588 Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - FMan MDIO Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) =============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) FMan Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Due to the fact that the FMan is an aggregation of sub-engines (ports, MACs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) etc.) the FMan node will have child nodes for each of them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PROPERTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Value type: <stringlist>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Definition: Must include "fsl,fman"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) FMan version can be determined via FM_IP_REV_1 register in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) FMan block. The offset is 0xc4 from the beginning of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) Frame Processing Manager memory map (0xc3000 from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) beginning of the FMan node).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Definition: Specifies the index of the FMan unit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) The cell-index value may be used by the SoC, to identify the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) FMan unit in the SoC memory map. In the table below,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) there's a description of the cell-index use in each SoC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - P1023:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) register[bit] FMan unit cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) ============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) DEVDISR[1] 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - P2041, P3041, P4080 P5020, P5040:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) register[bit] FMan unit cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) DCFG_DEVDISR2[6] 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) DCFG_DEVDISR2[14] 2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) (Second FM available only in P4080 and P5040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - B4860, T1040, T2080, T4240:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) register[bit] FMan unit cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) ============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) DCFG_CCSR_DEVDISR2[24] 1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) DCFG_CCSR_DEVDISR2[25] 2 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) (Second FM available only in T4240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) DEVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) the specific SoC "Device Configuration/Pin Control" Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) Map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Definition: A standard property. Specifies the offset of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) following configuration registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) - BMI configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) - QMI configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) - DMA configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) - FPM configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) - FMan controller configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) - ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) Definition: A standard property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) Definition: phandle for the fman input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Value type: <stringlist>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Definition: "fmanclk" for the fman input clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) Definition: A pair of IRQs are specified in this property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) The first element is associated with the event interrupts and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) the second element is associated with the error interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) - fsl,qman-channel-range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Definition: Specifies the range of the available dedicated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) channels in the FMan. The first cell specifies the beginning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) of the range and the second cell specifies the number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) Further information available at:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) "Work Queue (WQ) Channel Assignments in the QMan" section
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) in DPAA Reference Manual.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) - fsl,qman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) - fsl,bman
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) Definition: See soc/fsl/qman.txt and soc/fsl/bman.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) - fsl,erratum-a050385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) Usage: optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Value type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) Definition: A boolean property. Indicates the presence of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) erratum A050385 which indicates that DMA transactions that are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) split can result in a FMan lock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) =============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) FMan MURAM Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) FMan Internal memory - shared between all the FMan modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) It contains data structures that are common and written to or read by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) the modules.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FMan internal memory is split into the following parts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) Packet buffering (Tx/Rx FIFOs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) Frames internal context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PROPERTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) Value type: <stringlist>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) Definition: Must include "fsl,fman-muram"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) - ranges
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) Definition: A standard property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) Specifies the multi-user memory offset and the size within
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) the FMan.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) muram@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) compatible = "fsl,fman-muram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ranges = <0 0x000000 0x28000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) =============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) FMan Port Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) The Frame Manager (FMan) supports several types of hardware ports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) Ethernet receiver (RX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) Ethernet transmitter (TX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) Offline/Host command (O/H)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) PROPERTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) Value type: <stringlist>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) Definition: A standard property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) Must include one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) - "fsl,fman-v2-port-oh" for FManV2 OH ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) - "fsl,fman-v2-port-rx" for FManV2 RX ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) - "fsl,fman-v2-port-tx" for FManV2 TX ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) - "fsl,fman-v3-port-oh" for FManV3 OH ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) - "fsl,fman-v3-port-rx" for FManV3 RX ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) - "fsl,fman-v3-port-tx" for FManV3 TX ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) - cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) Definition: Specifies the hardware port id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) Each hardware port on the FMan has its own hardware PortID.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) Super set of all hardware Port IDs available at FMan Reference
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) Manual under "FMan Hardware Ports in Freescale Devices" table.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) Each hardware port is assigned a 4KB, port-specific page in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) the FMan hardware port memory region (which is part of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) FMan memory map). The first 4 KB in the FMan hardware ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) memory region is used for what are called common registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) The subsequent 63 4KB pages are allocated to the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) The page of a specific port is determined by the cell-index.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) Definition: There is one reg region describing the port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) configuration registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) - fsl,fman-10g-port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) Usage: optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) Value type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) Definition: The default port rate is 1G.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) If this property exists, the port is s 10G port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) - fsl,fman-best-effort-port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) Usage: optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) Value type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) Definition: Can be defined only if 10G-support is set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) This property marks a best-effort 10G port (10G port that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) may not be capable of line rate).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) port@a8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) cell-index = <0x28>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) compatible = "fsl,fman-v2-port-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) reg = <0xa8000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) port@88000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) cell-index = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) compatible = "fsl,fman-v2-port-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) reg = <0x88000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) port@81000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) cell-index = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) compatible = "fsl,fman-v2-port-oh";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) reg = <0x81000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) =============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) FMan dTSEC/XGEC/mEMAC Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) mEMAC/dTSEC/XGEC are the Ethernet network interfaces
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) PROPERTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) Value type: <stringlist>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) Definition: A standard property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) Must include one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) - "fsl,fman-dtsec" for dTSEC MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) - "fsl,fman-xgec" for XGEC MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) - "fsl,fman-memac" for mEMAC MAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) - cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) Definition: Specifies the MAC id.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) The cell-index value may be used by the FMan or the SoC, to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) identify the MAC unit in the FMan (or SoC) memory map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) In the tables below there's a description of the cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) use, there are two tables, one describes the use of cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) by the FMan, the second describes the use by the SoC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 1. FMan Registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) FManV2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) register[bit] MAC cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) ============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) FM_EPI[16] XGEC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) FM_EPI[16+n] dTSECn n-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) FM_NPI[11+n] dTSECn n-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) n = 1,..,5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) FManV3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) register[bit] MAC cell-index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) ============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) FM_EPI[16+n] mEMACn n-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) FM_EPI[25] mEMAC10 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) FM_NPI[11+n] mEMACn n-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) FM_NPI[10] mEMAC10 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) FM_NPI[11] mEMAC9 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) n = 1,..8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) FM_EPI and FM_NPI are located in the FMan memory map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 2. SoC registers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) - P2041, P3041, P4080 P5020, P5040:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) register[bit] FMan MAC cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) Unit index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) ============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) DCFG_DEVDISR2[7] 1 XGEC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) DCFG_DEVDISR2[7+n] 1 dTSECn n-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) DCFG_DEVDISR2[15] 2 XGEC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DCFG_DEVDISR2[15+n] 2 dTSECn n-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) n = 1,..5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) - T1040, T2080, T4240, B4860:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) register[bit] FMan MAC cell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) Unit index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ============================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DCFG_CCSR_DEVDISR2[n-1] 1 mEMACn n-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) DCFG_CCSR_DEVDISR2[11+n] 2 mEMACn n-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) n = 1,..6,9,10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) EVDISR, DCFG_DEVDISR2 and DCFG_CCSR_DEVDISR2 are located in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) the specific SoC "Device Configuration/Pin Control" Memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) Map.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) Definition: A standard property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) - fsl,fman-ports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) Definition: An array of two phandles - the first references is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) the FMan RX port and the second is the TX port used by this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) MAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) - ptp-timer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) Usage required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) Value type: <phandle>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) Definition: A phandle for 1EEE1588 timer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) - pcsphy-handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) Usage required for "fsl,fman-memac" MACs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) Value type: <phandle>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) Definition: A phandle for pcsphy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) - tbi-handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) Usage required for "fsl,fman-dtsec" MACs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) Value type: <phandle>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) Definition: A phandle for tbiphy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) fman1_tx28: port@a8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) cell-index = <0x28>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) compatible = "fsl,fman-v2-port-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) reg = <0xa8000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) fman1_rx8: port@88000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) cell-index = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) compatible = "fsl,fman-v2-port-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) reg = <0x88000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) ptp-timer: ptp_timer@fe000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) compatible = "fsl,fman-ptp-timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) reg = <0xfe000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ethernet@e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) compatible = "fsl,fman-dtsec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) cell-index = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) reg = <0xe0000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) fsl,fman-ports = <&fman1_rx8 &fman1_tx28>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) ptp-timer = <&ptp-timer>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) tbi-handle = <&tbi0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) FMan IEEE 1588 Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) Refer to Documentation/devicetree/bindings/ptp/ptp-qoriq.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) =============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) FMan MDIO Node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DESCRIPTION
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) The MDIO is a bus to which the PHY devices are connected.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) PROPERTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) Value type: <stringlist>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) Definition: A standard property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) Must include "fsl,fman-mdio" for 1 Gb/s MDIO from FMan v2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) Must include "fsl,fman-xmdio" for 10 Gb/s MDIO from FMan v2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) Must include "fsl,fman-memac-mdio" for 1/10 Gb/s MDIO from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) FMan v3.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) Usage: required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) Definition: A standard property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) - bus-frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) Usage: optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) Value type: <u32>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) Definition: Specifies the external MDIO bus clock speed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) be used, if different from the standard 2.5 MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) This may be due to the standard speed being unsupported (e.g.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) due to a hardware problem), or to advertise that all relevant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) components in the system support a faster speed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) Usage: required for external MDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) Value type: <prop-encoded-array>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) Definition: Event interrupt of external MDIO controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) - fsl,fman-internal-mdio
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) Usage: required for internal MDIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) Value type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) Definition: Fman has internal MDIO for internal PCS(Physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) Coding Sublayer) PHYs and external MDIO for external PHYs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) The settings and programming routines for internal/external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) MDIO are different. Must be included for internal MDIO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) - fsl,erratum-a011043
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) Usage: optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) Value type: <boolean>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) Definition: Indicates the presence of the A011043 erratum
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) describing that the MDIO_CFG[MDIO_RD_ER] bit may be falsely
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) set when reading internal PCS registers. MDIO reads to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) internal PCS registers may result in having the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) MDIO_CFG[MDIO_RD_ER] bit set, even when there is no error and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) read data (MDIO_DATA[MDIO_DATA]) is correct.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) Software may get false read error when reading internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) PCS registers through MDIO. As a workaround, all internal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) MDIO accesses should ignore the MDIO_CFG[MDIO_RD_ER] bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) For internal PHY device on internal mdio bus, a PHY node should be created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) See the definition of the PHY node in booting-without-of.txt for an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) example of how to define a PHY (Internal PHY has no interrupt line).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) - For "fsl,fman-mdio" compatible internal mdio bus, the PHY is TBI PHY.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) - For "fsl,fman-memac-mdio" compatible internal mdio bus, the PHY is PCS PHY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) PCS PHY addr must be '0'.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) EXAMPLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) Example for FMan v2 external MDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) mdio@f1000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) compatible = "fsl,fman-xmdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) reg = <0xf1000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) interrupts = <101 2 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) Example for FMan v2 internal MDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) mdio@e3120 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) compatible = "fsl,fman-mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) reg = <0xe3120 0xee0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) fsl,fman-internal-mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) tbi1: tbi-phy@8 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) reg = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) device_type = "tbi-phy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) Example for FMan v3 internal MDIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) mdio@f1000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) compatible = "fsl,fman-memac-mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) reg = <0xf1000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) fsl,fman-internal-mdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) pcsphy6: ethernet-phy@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) =============================================================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) Example
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) fman@400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) cell-index = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) compatible = "fsl,fman"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) ranges = <0 0x400000 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) reg = <0x400000 0x100000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) clocks = <&fman_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) clock-names = "fmanclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) interrupts = <
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 96 2 0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 16 2 1 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) fsl,qman-channel-range = <0x40 0xc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) muram@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) compatible = "fsl,fman-muram";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) reg = <0x0 0x28000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) port@81000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) cell-index = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) compatible = "fsl,fman-v2-port-oh";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) reg = <0x81000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) port@82000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) cell-index = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) compatible = "fsl,fman-v2-port-oh";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) reg = <0x82000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) port@83000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) cell-index = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) compatible = "fsl,fman-v2-port-oh";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) reg = <0x83000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) port@84000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) cell-index = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) compatible = "fsl,fman-v2-port-oh";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) reg = <0x84000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) port@85000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cell-index = <5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) compatible = "fsl,fman-v2-port-oh";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) reg = <0x85000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) port@86000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cell-index = <6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) compatible = "fsl,fman-v2-port-oh";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) reg = <0x86000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) fman1_rx_0x8: port@88000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) cell-index = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) compatible = "fsl,fman-v2-port-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) reg = <0x88000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) fman1_rx_0x9: port@89000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) cell-index = <0x9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) compatible = "fsl,fman-v2-port-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) reg = <0x89000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) fman1_rx_0xa: port@8a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) cell-index = <0xa>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) compatible = "fsl,fman-v2-port-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) reg = <0x8a000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) fman1_rx_0xb: port@8b000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) cell-index = <0xb>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) compatible = "fsl,fman-v2-port-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) reg = <0x8b000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) fman1_rx_0xc: port@8c000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cell-index = <0xc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) compatible = "fsl,fman-v2-port-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) reg = <0x8c000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) fman1_rx_0x10: port@90000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cell-index = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) compatible = "fsl,fman-v2-port-rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) reg = <0x90000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) fman1_tx_0x28: port@a8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) cell-index = <0x28>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) compatible = "fsl,fman-v2-port-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) reg = <0xa8000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) fman1_tx_0x29: port@a9000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) cell-index = <0x29>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) compatible = "fsl,fman-v2-port-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) reg = <0xa9000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) fman1_tx_0x2a: port@aa000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) cell-index = <0x2a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) compatible = "fsl,fman-v2-port-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) reg = <0xaa000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) fman1_tx_0x2b: port@ab000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) cell-index = <0x2b>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) compatible = "fsl,fman-v2-port-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) reg = <0xab000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) fman1_tx_0x2c: port@ac0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) cell-index = <0x2c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) compatible = "fsl,fman-v2-port-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) reg = <0xac000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) fman1_tx_0x30: port@b0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) cell-index = <0x30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) compatible = "fsl,fman-v2-port-tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) reg = <0xb0000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) ethernet@e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) compatible = "fsl,fman-dtsec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) cell-index = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) reg = <0xe0000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) fsl,fman-ports = <&fman1_rx_0x8 &fman1_tx_0x28>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) tbi-handle = <&tbi5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ethernet@e2000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) compatible = "fsl,fman-dtsec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) cell-index = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) reg = <0xe2000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) fsl,fman-ports = <&fman1_rx_0x9 &fman1_tx_0x29>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) tbi-handle = <&tbi6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) ethernet@e4000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) compatible = "fsl,fman-dtsec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) cell-index = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) reg = <0xe4000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) fsl,fman-ports = <&fman1_rx_0xa &fman1_tx_0x2a>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tbi-handle = <&tbi7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) ethernet@e6000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) compatible = "fsl,fman-dtsec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) cell-index = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) reg = <0xe6000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) fsl,fman-ports = <&fman1_rx_0xb &fman1_tx_0x2b>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tbi-handle = <&tbi8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ethernet@e8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) compatible = "fsl,fman-dtsec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) cell-index = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) reg = <0xf0000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) fsl,fman-ports = <&fman1_rx_0xc &fman1_tx_0x2c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) tbi-handle = <&tbi9>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) ethernet@f0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) cell-index = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) compatible = "fsl,fman-xgec";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) reg = <0xf0000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) fsl,fman-ports = <&fman1_rx_0x10 &fman1_tx_0x30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) ptp-timer@fe000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) compatible = "fsl,fman-ptp-timer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) reg = <0xfe000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mdio@f1000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) compatible = "fsl,fman-xmdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) reg = <0xf1000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) interrupts = <101 2 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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