^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * ENETC ethernet device tree bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Depending on board design and ENETC port type (internal or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) external) there are two supported link modes specified by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) below device tree bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - reg : Specifies PCIe Device Number and Function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Number of the ENETC endpoint device, according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) to parent node bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - compatible : Should be "fsl,enetc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 1. The ENETC external port is connected to a MDIO configurable phy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 1.1. Using the local ENETC Port MDIO interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) In this case, the ENETC node should include a "mdio" sub-node
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) that in turn should contain the "ethernet-phy" node describing the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) external phy. Below properties are required, their bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) already defined in Documentation/devicetree/bindings/net/ethernet.txt or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Documentation/devicetree/bindings/net/phy.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - phy-handle : Phandle to a PHY on the MDIO bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Defined in ethernet.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - phy-connection-type : Defined in ethernet.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - mdio : "mdio" node, defined in mdio.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - ethernet-phy : "ethernet-phy" node, defined in phy.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) ethernet@0,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) compatible = "fsl,enetc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) reg = <0x000000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) phy-handle = <&sgmii_phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) phy-connection-type = "sgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) mdio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) sgmii_phy0: ethernet-phy@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) reg = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 1.2. Using the central MDIO PCIe endpoint device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) In this case, the mdio node should be defined as another PCIe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) endpoint node, at the same level with the ENETC port nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) - reg : Specifies PCIe Device Number and Function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Number of the ENETC endpoint device, according
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) to parent node bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - compatible : Should be "fsl,enetc-mdio".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) The remaining required mdio bus properties are standard, their bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) already defined in Documentation/devicetree/bindings/net/mdio.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ethernet@0,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) compatible = "fsl,enetc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) reg = <0x000000 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) phy-handle = <&sgmii_phy0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) phy-connection-type = "sgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mdio@0,3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) compatible = "fsl,enetc-mdio";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg = <0x000300 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) sgmii_phy0: ethernet-phy@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) reg = <0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) 2. The ENETC port is an internal port or has a fixed-link external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) connection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) In this case, the ENETC port node defines a fixed link connection,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) as specified by Documentation/devicetree/bindings/net/fixed-link.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) Required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) - fixed-link : "fixed-link" node, defined in "fixed-link.txt".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) ethernet@0,2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) compatible = "fsl,enetc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) reg = <0x000200 0 0 0 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) fixed-link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) speed = <1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) full-duplex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags