^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * AMD 10GbE driver (amd-xgbe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: Should be "amd,xgbe-seattle-v1a"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) - reg: Address and length of the register sets for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) - MAC registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - PCS registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - SerDes Rx/Tx registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - SerDes integration registers (1/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - SerDes integration registers (2/2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - interrupts: Should contain the amd-xgbe interrupt(s). The first interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) listed is required and is the general device interrupt. If the optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) amd,per-channel-interrupt property is specified, then one additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) interrupt for each DMA channel supported by the device should be specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) The last interrupt listed should be the PCS auto-negotiation interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - DMA clock for the amd-xgbe device (used for calculating the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) correct Rx interrupt watchdog timer value on a DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) for coalescing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - PTP clock for the amd-xgbe device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - clock-names: Should be the names of the clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - "dma_clk" for the DMA clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - "ptp_clk" for the PTP clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - phy-mode: See ethernet.txt file in the same directory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - dma-coherent: Present if dma operations are coherent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - amd,per-channel-interrupt: Indicates that Rx and Tx complete will generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) a unique interrupt for each DMA channel - this requires an additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) interrupt be configured for each DMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - amd,speed-set: Speed capabilities of the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 0 - 1GbE and 10GbE (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 1 - 2.5GbE and 10GbE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) The MAC address will be determined using the optional properties defined in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ethernet.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) The following optional properties are represented by an array with each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) value corresponding to a particular speed. The first array value represents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) the setting for the 1GbE speed, the second value for the 2.5GbE speed and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) the third value for the 10GbE speed. All three values are required if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) property is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - amd,serdes-blwc: Baseline wandering correction enablement
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 0 - Off
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 1 - On
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - amd,serdes-cdr-rate: CDR rate speed selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - amd,serdes-pq-skew: PQ (data sampling) skew
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - amd,serdes-tx-amp: TX amplitude boost
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - amd,serdes-dfe-tap-config: DFE taps available to run
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - amd,serdes-dfe-tap-enable: DFE taps to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) xgbe@e0700000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) compatible = "amd,xgbe-seattle-v1a";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg = <0 0xe0700000 0 0x80000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) <0 0xe0780000 0 0x80000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) <0 0xe1240800 0 0x00400>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) <0 0xe1250000 0 0x00060>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) <0 0xe1250080 0 0x00004>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) interrupt-parent = <&gic>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) interrupts = <0 325 4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) <0 326 1>, <0 327 1>, <0 328 1>, <0 329 1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) <0 323 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) amd,per-channel-interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clocks = <&xgbe_dma_clk>, <&xgbe_ptp_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) clock-names = "dma_clk", "ptp_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) phy-mode = "xgmii";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) mac-address = [ 02 a1 a2 a3 a4 a5 ];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) amd,speed-set = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) amd,serdes-blwc = <1>, <1>, <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) amd,serdes-cdr-rate = <2>, <2>, <7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) amd,serdes-pq-skew = <10>, <10>, <30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) amd,serdes-tx-amp = <15>, <15>, <10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) amd,serdes-dfe-tap-config = <3>, <3>, <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) amd,serdes-dfe-tap-enable = <0>, <0>, <127>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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