^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Generic register bitfield-based multiplexer controller bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Define register bitfields to be used to control multiplexers. The parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) device tree node must be a device node to provide register r/w access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible : should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) "reg-mux" : if parent device of mux controller is not syscon device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "mmio-mux" : if parent device of mux controller is syscon device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #mux-control-cells : <1>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - mux-reg-masks : an array of register offset and pre-shifted bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) pairs, each describing a single mux control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Standard mux-controller bindings as decribed in mux-controller.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - idle-states : if present, the state the muxes will have when idle. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) special state MUX_IDLE_AS_IS is the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) The multiplexer state of each multiplexer is defined as the value of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) bitfield described by the corresponding register offset and bitfield mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) pair in the mux-reg-masks array.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) The parent device of mux controller is not a syscon device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) &i2c0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) fpga@66 { // fpga connected to i2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) compatible = "fsl,lx2160aqds-fpga", "fsl,fpga-qixis-i2c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "simple-mfd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) reg = <0x66>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) mux: mux-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) compatible = "reg-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #mux-control-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) mux-reg-masks = <0x54 0xf8>, /* 0: reg 0x54, bits 7:3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) <0x54 0x07>; /* 1: reg 0x54, bits 2:0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) mdio-mux-1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) compatible = "mdio-mux-multiplexer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) mux-controls = <&mux 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) mdio-parent-bus = <&emdio1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) mdio@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) mdio@8 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) reg = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mdio-mux-2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) compatible = "mdio-mux-multiplexer";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) mux-controls = <&mux 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) mdio-parent-bus = <&emdio2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) mdio@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) reg = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mdio@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) reg = <0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ..
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) Example 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) The parent device of mux controller is syscon device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) syscon {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) compatible = "syscon";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mux: mux-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) compatible = "mmio-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #mux-control-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) mux-reg-masks = <0x3 0x30>, /* 0: reg 0x3, bits 5:4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) <0x3 0x40>, /* 1: reg 0x3, bit 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) idle-states = <MUX_IDLE_AS_IS>, <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) video-mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) compatible = "video-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) mux-controls = <&mux 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) ports {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* inputs 0..3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) port@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) port@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) port@2 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) reg = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) port@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /* output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) port@4 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) reg = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) };
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