Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) GPIO-based multiplexer controller bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Define what GPIO pins are used to control a multiplexer. Or several
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) multiplexers, if the same pins control more than one multiplexer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - compatible : "gpio-mux"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - mux-gpios : list of gpios used to control the multiplexer, least
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	      significant bit first.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #mux-control-cells : <0>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Standard mux-controller bindings as decribed in mux-controller.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - idle-state : if present, the state the mux will have when idle. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	       special state MUX_IDLE_AS_IS is the default.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) The multiplexer state is defined as the number represented by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) multiplexer GPIO pins, where the first pin is the least significant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) bit. An active pin is a binary 1, an inactive pin is a binary 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	mux: mux-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		compatible = "gpio-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		#mux-control-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		mux-gpios = <&pioA 0 GPIO_ACTIVE_HIGH>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 			    <&pioA 1 GPIO_ACTIVE_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	adc-mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		compatible = "io-channel-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		io-channels = <&adc 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		io-channel-names = "parent";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		mux-controls = <&mux>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		channels = "sync-1", "in", "out", "sync-2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	i2c-mux {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		compatible = "i2c-mux";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		i2c-parent = <&i2c1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		mux-controls = <&mux>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		i2c@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			ssd1307: oled@3c {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 				/* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		i2c@3 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			reg = <3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 			#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 			pca9555: pca9555@20 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 				/* ... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 			};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 	};