^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Freescale's NAND flash controller (NFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This variant of the Freescale NAND flash controller (NFC) can be found on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Vybrid (vf610), MPC5125, MCF54418 and Kinetis K70.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible: Should be set to "fsl,vf610-nfc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - reg: address range of the NFC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - interrupts: interrupt of the NFC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - #address-cells: shall be set to 1. Encode the nand CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - #size-cells : shall be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - assigned-clocks: main clock from the SoC, for Vybrid <&clks VF610_CLK_NFC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - assigned-clock-rates: The NAND bus timing is derived from this clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) rate and should not exceed maximum timing for any NAND memory chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) in a board stuffing. Typical NAND memory timings derived from this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) clock are found in the SoC hardware reference manual. Furthermore,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) there might be restrictions on maximum rates when using hardware ECC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - #address-cells, #size-cells : Must be present if the device has sub-nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) representing partitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Required children nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Children nodes represent the available nand chips. Currently the driver can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) only handle one NAND chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - compatible: Should be set to "fsl,vf610-nfc-cs".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - nand-bus-width: see nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - nand-ecc-mode: see nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Required properties for hardware ECC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - nand-ecc-strength: supported strengths are 24 and 32 bit (see nand-controller.yaml)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - nand-ecc-step-size: step size equals page size, currently only 2k pages are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) supported
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - nand-on-flash-bbt: see nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) nfc: nand@400e0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) compatible = "fsl,vf610-nfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) reg = <0x400e0000 0x4000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) clocks = <&clks VF610_CLK_NFC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) clock-names = "nfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) assigned-clocks = <&clks VF610_CLK_NFC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) assigned-clock-rates = <33000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) nand@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) compatible = "fsl,vf610-nfc-nandcs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) nand-bus-width = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) nand-ecc-mode = "hw";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) nand-ecc-strength = <32>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) nand-ecc-step-size = <2048>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) nand-on-flash-bbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };