Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * NXP SPI Flash Interface (SPIFI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) NXP SPIFI is a specialized SPI interface for serial Flash devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) It supports one Flash device with 1-, 2- and 4-bits width in SPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) mode 0 or 3. The controller operates in either command or memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) mode. In memory mode the Flash is accessible from the CPU as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) normal memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - compatible : Should be "nxp,lpc1773-spifi"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - reg : the first contains the register location and length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)           the second contains the memory mapping address and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - reg-names: Should contain the reg names "spifi" and "flash"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   - interrupts : Should contain the interrupt for the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - clocks : The clocks needed by the SPIFI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   - clock-names : Should contain the clock names "spifi" and "reg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)  - resets : phandle + reset specifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) The SPI Flash must be a child of the SPIFI node and must have a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) compatible property as specified in bindings/mtd/jedec,spi-nor.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Optionally it can also contain the following properties.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)  - spi-cpol : Controller only supports mode 0 and 3 so either
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)               both spi-cpol and spi-cpha should be present or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)               none of them
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)  - spi-cpha : See above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)  - spi-rx-bus-width : Used to select how many pins that are used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)                       for input on the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) See bindings/spi/spi-bus.txt for more information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) spifi: spifi@40003000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	compatible = "nxp,lpc1773-spifi";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	reg = <0x40003000 0x1000>, <0x14000000 0x4000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	reg-names = "spifi", "flash";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	interrupts = <30>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	clocks = <&ccu1 CLK_SPIFI>, <&ccu1 CLK_CPU_SPIFI>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	clock-names = "spifi", "reg";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	resets = <&rgu 53>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	flash@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		compatible = "jedec,spi-nor";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		spi-cpol;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		spi-cpha;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		spi-rx-bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 			label = "data";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 			reg = <0 0x200000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)