Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) NVIDIA Tegra NAND Flash controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: Must be one of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   - "nvidia,tegra20-nand"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg: MMIO address range
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - interrupts: interrupt output of the NFC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - clocks: Must contain an entry for each entry in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   See ../clocks/clock-bindings.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clock-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - nand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - resets: Must contain an entry for each entry in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - reset-names: Must include the following entries:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - nand
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional children nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Individual NAND chips are children of the NAND controller node. Currently
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) only one NAND chip supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Required children node properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - reg: An integer ranging from 1 to 6 representing the CS line to use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Optional children node properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		 "hw" is supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - nand-ecc-algo: string, algorithm of NAND ECC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		 Supported values with "hw" ECC mode are: "rs", "bch".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - nand-bus-width : See nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - nand-on-flash-bbt: See nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - nand-ecc-strength: integer representing the number of bits to correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		     per ECC step (always 512). Supported strength using HW ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		     modes are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		     - RS: 4, 6, 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		     - BCH: 4, 8, 14, 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - nand-ecc-maximize: See nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		       are chosen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - wp-gpios: GPIO specifier for the write protect pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Optional child node of NAND chip nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Partitions: see partition.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)   Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	nand-controller@70008000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		compatible = "nvidia,tegra20-nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		reg = <0x70008000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		clock-names = "nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		resets = <&tegra_car 13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		reset-names = "nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		nand@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 			#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 			#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			nand-bus-width = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 			nand-on-flash-bbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			nand-ecc-algo = "bch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			nand-ecc-strength = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 	};