^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) $id: http://devicetree.org/schemas/mtd/nand-controller.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) title: NAND Chip and NAND Controller Generic Binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - Miquel Raynal <miquel.raynal@bootlin.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Richard Weinberger <richard@nod.at>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) The NAND controller should be represented with its own DT node, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) all NAND chips attached to this controller should be defined as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) children nodes of the NAND controller. This representation should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enforced even for simple controllers supporting only one chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) The ECC strength and ECC step size properties define the user
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) desires in terms of correction capability of a controller. Together,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) they request the ECC engine to correct {strength} bit errors per
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) {size} bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) The interpretation of these parameters is implementation-defined, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) not all implementations must support all possible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) combinations. However, implementations are encouraged to further
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) specify the value(s) they support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) $nodename:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) pattern: "^nand-controller(@.*)?"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "#address-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) const: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "#size-cells":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) const: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) ranges: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) patternProperties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "^nand@[a-f0-9]$":
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) type: object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Contains the chip-select IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) nand-ecc-mode:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Desired ECC engine, either hardware (most of the time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) embedded in the NAND controller) or software correction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) (Linux will handle the calculations). soft_bch is deprecated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) and should be replaced by soft and nand-ecc-algo.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) $ref: /schemas/types.yaml#/definitions/string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) enum: [none, soft, hw, hw_syndrome, hw_oob_first, on-die]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) nand-ecc-engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) - $ref: /schemas/types.yaml#/definitions/phandle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) description: |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) A phandle on the hardware ECC engine if any. There are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) basically three possibilities:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 1/ The ECC engine is part of the NAND controller, in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) case the phandle should reference the parent node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 2/ The ECC engine is part of the NAND part (on-die), in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) case the phandle should reference the node itself.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 3/ The ECC engine is external, in this case the phandle should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) reference the specific ECC engine node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) nand-use-soft-ecc-engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) description: Use a software ECC engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) nand-no-ecc-engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) type: boolean
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) description: Do not use any ECC correction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) nand-ecc-placement:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) - $ref: /schemas/types.yaml#/definitions/string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) - enum: [ oob, interleaved ]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) Location of the ECC bytes. This location is unknown by default
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) but can be explicitly set to "oob", if all ECC bytes are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) known to be stored in the OOB area, or "interleaved" if ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) bytes will be interleaved with regular data in the main area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) nand-ecc-algo:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) Desired ECC algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) $ref: /schemas/types.yaml#/definitions/string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) enum: [hamming, bch, rs]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) nand-bus-width:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) Bus width to the NAND chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) enum: [8, 16]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) default: 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) nand-on-flash-bbt:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) $ref: /schemas/types.yaml#/definitions/flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) With this property, the OS will search the device for a Bad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) Block Table (BBT). If not found, it will create one, reserve
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) a few blocks at the end of the device to store it and update
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) it as the device ages. Otherwise, the out-of-band area of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) few pages of all the blocks will be scanned at boot time to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) find Bad Block Markers (BBM). These markers will help to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) build a volatile BBT in RAM.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) nand-ecc-strength:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) Maximum number of bits that can be corrected per ECC step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) minimum: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) nand-ecc-step-size:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) Number of data bytes covered by a single ECC step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) minimum: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) nand-ecc-maximize:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) $ref: /schemas/types.yaml#/definitions/flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) Whether or not the ECC strength should be maximized. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) maximum ECC strength is both controller and chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dependent. The ECC engine has to select the ECC config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) providing the best strength and taking the OOB area size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) constraint into account. This is particularly useful when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) only the in-band area is used by the upper layers, and you
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) want to make your NAND as reliable as possible.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) nand-is-boot-medium:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) $ref: /schemas/types.yaml#/definitions/flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) Whether or not the NAND chip is a boot medium. Drivers might
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) use this information to select ECC algorithms supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) the boot ROM or similar restrictions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) nand-rb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) $ref: /schemas/types.yaml#/definitions/uint32-array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) Contains the native Ready/Busy IDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) rb-gpios:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) Contains one or more GPIO descriptor (the numper of descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) depends on the number of R/B pins exposed by the flash) for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) Ready/Busy pins. Active state refers to the NAND ready state and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) should be set to GPIOD_ACTIVE_HIGH unless the signal is inverted.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) - "#address-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) - "#size-cells"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) additionalProperties: true
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) nand-controller {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* controller specific properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) nand@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) nand-ecc-mode = "soft";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) nand-ecc-algo = "bch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* NAND chip specific properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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