Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Macronix Raw NAND Controller Device Tree Bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) -------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible: should be "mxic,multi-itfc-v009-nand-controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg: should contain 1 entry for the registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - #address-cells: should be set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - #size-cells: should be set to 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - interrupts: interrupt line connected to this raw NAND controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clock-names: should contain "ps", "send" and "send_dly"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - clocks: should contain 3 phandles for the "ps", "send" and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	 "send_dly" clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Children nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - children nodes represent the available NAND chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) See Documentation/devicetree/bindings/mtd/nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) for more details on generic bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	nand: nand-controller@43c30000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		compatible = "mxic,multi-itfc-v009-nand-controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		reg = <0x43c30000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		interrupts = <GIC_SPI 0x1d IRQ_TYPE_EDGE_RISING>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		clocks = <&clkwizard 0>, <&clkwizard 1>, <&clkc 15>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		clock-names = "send", "send_dly", "ps";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		nand@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 			nand-ecc-mode = "soft";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 			nand-ecc-algo = "bch";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	};