^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) MTK SoCs NAND FLASH controller (NFC) DT binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This file documents the device tree bindings for MTK SoCs NAND controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The functional split of the controller requires two drivers to operate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) the nand controller interface driver and the ECC engine driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) The hardware description for both devices must be captured as device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) tree nodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 1) NFC NAND Controller Interface (NFI):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) =======================================
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) The first part of NFC is NAND Controller Interface (NFI) HW.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Required NFI properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - compatible: Should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "mediatek,mt2701-nfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "mediatek,mt2712-nfc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "mediatek,mt7622-nfc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - reg: Base physical address and size of NFI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - interrupts: Interrupts of NFI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - clocks: NFI required clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - clock-names: NFI clocks internal name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - ecc-engine: Required ECC Engine node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - #address-cells: NAND chip index, should be 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - #size-cells: Should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) nandc: nfi@1100d000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) compatible = "mediatek,mt2701-nfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) reg = <0 0x1100d000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) clocks = <&pericfg CLK_PERI_NFI>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) <&pericfg CLK_PERI_NFI_PAD>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) clock-names = "nfi_clk", "pad_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) ecc-engine = <&bch>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Platform related properties, should be set in {platform_name}.dts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - children nodes: NAND chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Children nodes properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - reg: Chip Select Signal, default 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) Set as reg = <0>, <1> when need 2 CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Optional:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - nand-on-flash-bbt: Store BBT on NAND Flash.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - nand-ecc-mode: the NAND ecc mode (check driver for supported modes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - nand-ecc-step-size: Number of data bytes covered by a single ECC step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) valid values:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 512 and 1024 on mt2701 and mt2712.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 512 only on mt7622.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 1024 is recommended for large page NANDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - nand-ecc-strength: Number of bits to correct per ECC step.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) The valid values that each controller supports:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mt2701: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 32, 36, 40, 44, 48, 52, 56, 60.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) mt2712: 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 32, 36, 40, 44, 48, 52, 56, 60, 68, 72, 80.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) mt7622: 4, 6, 8, 10, 12, 14, 16.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) The strength should be calculated as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) E = (S - F) * 8 / B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) S = O / (P / Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) E : nand-ecc-strength.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) S : spare size per sector.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) F : FDM size, should be in the range [1,8].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) It is used to store free oob data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) O : oob size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) P : page size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) Q : nand-ecc-step-size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) B : number of parity bits needed to correct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 1 bitflip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) According to MTK NAND controller design,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) this number depends on max ecc step size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) that MTK NAND controller supports.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) If max ecc step size supported is 1024,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) then it should be always 14. And if max
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ecc step size is 512, then it should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) always 13.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) If the result does not match any one of the listed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) choices above, please select the smaller valid value from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) (otherwise the driver will do the adjustment at runtime)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) - pinctrl-names: Default NAND pin GPIO setting name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) - pinctrl-0: GPIO setting node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) &pio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) nand_pins_default: nanddefault {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) pins_dat {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pinmux = <MT2701_PIN_111_MSDC0_DAT7__FUNC_NLD7>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) <MT2701_PIN_112_MSDC0_DAT6__FUNC_NLD6>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) <MT2701_PIN_114_MSDC0_DAT4__FUNC_NLD4>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) <MT2701_PIN_118_MSDC0_DAT3__FUNC_NLD3>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) <MT2701_PIN_121_MSDC0_DAT0__FUNC_NLD0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) <MT2701_PIN_120_MSDC0_DAT1__FUNC_NLD1>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) <MT2701_PIN_113_MSDC0_DAT5__FUNC_NLD5>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) <MT2701_PIN_115_MSDC0_RSTB__FUNC_NLD8>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) <MT2701_PIN_119_MSDC0_DAT2__FUNC_NLD2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) input-enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) drive-strength = <MTK_DRIVE_8mA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) bias-pull-up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) pins_we {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pinmux = <MT2701_PIN_117_MSDC0_CLK__FUNC_NWEB>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) drive-strength = <MTK_DRIVE_8mA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bias-pull-up = <MTK_PUPD_SET_R1R0_10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) pins_ale {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pinmux = <MT2701_PIN_116_MSDC0_CMD__FUNC_NALE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) drive-strength = <MTK_DRIVE_8mA>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bias-pull-down = <MTK_PUPD_SET_R1R0_10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) &nandc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) pinctrl-0 = <&nand_pins_default>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) nand@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) nand-on-flash-bbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) nand-ecc-mode = "hw";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) nand-ecc-strength = <24>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) nand-ecc-step-size = <1024>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) NAND chip optional subnodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) nand@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) partitions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) compatible = "fixed-partitions";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) preloader@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) label = "pl";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) read-only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) reg = <0x00000000 0x00400000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) android@00400000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) label = "android";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) reg = <0x00400000 0x12c00000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 2) ECC Engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) ==============
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) Required BCH properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) - compatible: Should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) "mediatek,mt2701-ecc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) "mediatek,mt2712-ecc",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "mediatek,mt7622-ecc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) - reg: Base physical address and size of ECC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) - interrupts: Interrupts of ECC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) - clocks: ECC required clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) - clock-names: ECC clocks internal name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) bch: ecc@1100e000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) compatible = "mediatek,mt2701-ecc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) reg = <0 0x1100e000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) clocks = <&pericfg CLK_PERI_NFI_ECC>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) clock-names = "nfiecc_clk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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