^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Marvell NAND Flash Controller (NFC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) - compatible: can be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * "marvell,armada-8k-nand-controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * "marvell,armada370-nand-controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * "marvell,pxa3xx-nand-controller"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * "marvell,armada-8k-nand" (deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * "marvell,armada370-nand" (deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * "marvell,pxa3xx-nand" (deprecated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Compatibles marked deprecated support only the old bindings described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) at the bottom.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - reg: NAND flash controller memory area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - #address-cells: shall be set to 1. Encode the NAND CS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - #size-cells: shall be set to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - interrupts: shall define the NAND controller interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - clocks: shall reference the NAND controller clocks, the second one is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) is only needed for the Armada 7K/8K SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - clock-names: mandatory if there is a second clock, in this case there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) should be one clock named "core" and another one named "reg"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - marvell,system-controller: Set to retrieve the syscon node that handles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) NAND controller related registers (only required with the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "marvell,armada-8k-nand[-controller]" compatibles).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - label: see partition.txt. New platforms shall omit this property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - dmas: shall reference DMA channel associated to the NAND controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) This property is only used with "marvell,pxa3xx-nand[-controller]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) compatible strings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - dma-names: shall be "rxtx".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) This property is only used with "marvell,pxa3xx-nand[-controller]"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) compatible strings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) Optional children nodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Children nodes represent the available NAND chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - reg: shall contain the native Chip Select ids (0-3).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - nand-rb: see nand-controller.yaml (0-1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - marvell,nand-keep-config: orders the driver not to take the timings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) from the core and leaving them completely untouched. Bootloader
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) timings will then be used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - label: MTD name.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - nand-on-flash-bbt: see nand-controller.yaml.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) - nand-ecc-mode: see nand-controller.yaml. Will use hardware ECC if not specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - nand-ecc-algo: see nand-controller.yaml. This property is essentially useful when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) not using hardware ECC. Howerver, it may be added when using hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ECC for clarification but will be ignored by the driver because ECC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) mode is chosen depending on the page size and the strength required by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) the NAND chip. This value may be overwritten with nand-ecc-strength
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - nand-ecc-strength: see nand-controller.yaml.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - nand-ecc-step-size: see nand-controller.yaml. Marvell's NAND flash controller does
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) use fixed strength (1-bit for Hamming, 16-bit for BCH), so the actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) step size will shrink or grow in order to fit the required strength.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) Step sizes are not completely random for all and follow certain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) patterns described in AN-379, "Marvell SoC NFC ECC".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) generic bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) nand_controller: nand-controller@d0000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) compatible = "marvell,armada370-nand-controller";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) reg = <0xd0000 0x54>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clocks = <&coredivclk 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) nand@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) label = "main-storage";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) nand-rb = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) nand-ecc-mode = "hw";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) marvell,nand-keep-config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) nand-on-flash-bbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) nand-ecc-strength = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) nand-ecc-step-size = <512>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) partitions {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) compatible = "fixed-partitions";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) label = "Rootfs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) reg = <0x00000000 0x40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) Note on legacy bindings: One can find, in not-updated device trees,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) bindings slightly different than described above with other properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) described below as well as the partitions node at the root of a so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) called "nand" node (without clear controller/chip separation).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) Legacy properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) - marvell,nand-enable-arbiter: To enable the arbiter, all boards blindly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) used it, this bit was set by the bootloader for many boards and even if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) it is marked reserved in several datasheets, it might be needed to set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) it (otherwise it is harmless) so whether or not this property is set,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) the bit is selected by the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) - num-cs: Number of chip-select lines to use, all boards blindly set 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) to this and for a reason, other values would have failed. The value of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) this property is ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) nand0: nand@43100000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) compatible = "marvell,pxa3xx-nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) reg = <0x43100000 90>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) interrupts = <45>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dmas = <&pdma 97 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) dma-names = "rxtx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) marvell,nand-keep-config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) marvell,nand-enable-arbiter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) num-cs = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) /* Partitions (optional) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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