Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) NXP LPC32xx SoC NAND SLC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: "nxp,lpc3220-slc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Address and size of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - nand-on-flash-bbt: Use bad block table on flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - gpios: GPIO specification for NAND write protect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) The following required properties are very controller specific. See the LPC32xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) User Manual:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - nxp,wdr-clks: Delay before Ready signal is tested on write (W_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - nxp,rdr-clks: Delay before Ready signal is tested on read (R_RDY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) (The following values are specified in Hz, to make them independent of actual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) clock speed:)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - nxp,wwidth: Write pulse width (W_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - nxp,whold: Write hold time (W_HOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - nxp,wsetup: Write setup time (W_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - nxp,rwidth: Read pulse width (R_WIDTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - nxp,rhold: Read hold time (R_HOLD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - nxp,rsetup: Read setup time (R_SETUP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) Optional subnodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	slc: flash@20020000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		compatible = "nxp,lpc3220-slc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		reg = <0x20020000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		nxp,wdr-clks = <14>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		nxp,wwidth = <40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		nxp,whold = <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		nxp,wsetup = <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		nxp,rdr-clks = <14>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		nxp,rwidth = <40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		nxp,rhold = <66666666>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		nxp,rsetup = <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		nand-on-flash-bbt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		mtd0@00000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			label = "phy3250-boot";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			reg = <0x00000000 0x00064000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			read-only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	};