Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) NXP LPC32xx SoC NAND MLC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible: "nxp,lpc3220-mlc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg: Address and size of the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts: The NAND interrupt specification
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - gpios: GPIO specification for NAND write protect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) The following required properties are very controller specific. See the LPC32xx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) User Manual 7.5.14 MLC NAND Timing Register (the values here are specified in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Hz, to make them independent of actual clock speed and to provide for good
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) accuracy:)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - nxp,tcea_delay: TCEA_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - nxp,busy_delay: BUSY_DELAY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - nxp,nand_ta: NAND_TA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - nxp,rd_high: RD_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - nxp,rd_low: RD_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - nxp,wr_high: WR_HIGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - nxp,wr_low: WR_LOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Optional subnodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - Partitions, see Documentation/devicetree/bindings/mtd/partition.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	mlc: flash@200a8000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		compatible = "nxp,lpc3220-mlc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		reg = <0x200A8000 0x11000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		interrupts = <11 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		nxp,tcea-delay = <333333333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		nxp,busy-delay = <10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		nxp,nand-ta = <18181818>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		nxp,rd-high = <31250000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 		nxp,rd-low = <45454545>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		nxp,wr-high = <40000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		nxp,wr-low = <83333333>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		gpios = <&gpio 5 19 1>; /* GPO_P3 19, active low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		mtd0@00000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			label = "boot";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 			reg = <0x00000000 0x00064000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 			read-only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	};