^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) Device tree bindings for GPMC connected NANDs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) GPMC connected NAND (found on OMAP boards) are represented as child nodes of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) the GPMC controller with a name of "nand".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) All timing relevant properties as well as generic gpmc child properties are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) explained in a separate documents - please refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Documentation/devicetree/bindings/memory-controllers/omap-gpmc.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) For NAND specific properties such as ECC modes or bus width, please refer to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Documentation/devicetree/bindings/mtd/nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - compatible: "ti,omap2-nand"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - reg: range id (CS number), base offset and length of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) NAND I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - interrupts: Two interrupt specifiers, one for fifoevent, one for termcount.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - nand-bus-width: Set this numeric value to 16 if the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) is wired that way. If not specified, a bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) width of 8 is assumed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - ti,nand-ecc-opt: A string setting the ECC layout to use. One of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "sw" 1-bit Hamming ecc code via software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "hw" <deprecated> use "ham1" instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "hw-romcode" <deprecated> use "ham1" instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "ham1" 1-bit Hamming ecc code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "bch4" 4-bit BCH ecc code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "bch8" 8-bit BCH ecc code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "bch16" 16-bit BCH ECC code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Refer below "How to select correct ECC scheme for your device ?"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - ti,nand-xfer-type: A string setting the data transfer type. One of:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "prefetch-polled" Prefetch polled mode (default)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "polled" Polled mode, without prefetch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "prefetch-dma" Prefetch enabled DMA mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "prefetch-irq" Prefetch enabled irq mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - elm_id: <deprecated> use "ti,elm-id" instead
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - ti,elm-id: Specifies phandle of the ELM devicetree node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) ELM is an on-chip hardware engine on TI SoC which is used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) locating ECC errors for BCHx algorithms. SoC devices which have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ELM hardware engines should specify this device node in .dtsi
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) Using ELM for ECC error correction frees some CPU cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) - rb-gpios: GPIO specifier for the ready/busy# pin.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) For inline partition table parsing (optional):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - #address-cells: should be set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) - #size-cells: should be set to 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) Example for an AM33xx board:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) gpmc: gpmc@50000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) compatible = "ti,am3352-gpmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) ti,hwmods = "gpmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) reg = <0x50000000 0x36c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) interrupts = <100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) gpmc,num-cs = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) gpmc,num-waitpins = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) ranges = <0 0 0x08000000 0x1000000>; /* CS0 space, 16MB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) elm_id = <&elm>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) interrupt-controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #interrupt-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) nand@0,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) compatible = "ti,omap2-nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) reg = <0 0 4>; /* CS0, offset 0, NAND I/O window 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) interrupt-parent = <&gpmc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) interrupts = <0 IRQ_TYPE_NONE>, <1 IRQ_TYPE NONE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) nand-bus-width = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ti,nand-ecc-opt = "bch8";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) ti,nand-xfer-type = "polled";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) rb-gpios = <&gpmc 0 GPIO_ACTIVE_HIGH>; /* gpmc_wait0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) gpmc,sync-clk-ps = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) gpmc,cs-on-ns = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) gpmc,cs-rd-off-ns = <44>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) gpmc,cs-wr-off-ns = <44>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) gpmc,adv-on-ns = <6>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) gpmc,adv-rd-off-ns = <34>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) gpmc,adv-wr-off-ns = <44>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) gpmc,we-off-ns = <40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) gpmc,oe-off-ns = <54>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) gpmc,access-ns = <64>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) gpmc,rd-cycle-ns = <82>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) gpmc,wr-cycle-ns = <82>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) gpmc,wr-access-ns = <40>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) gpmc,wr-data-mux-bus-ns = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* partitions go here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) How to select correct ECC scheme for your device ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) --------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) Higher ECC scheme usually means better protection against bit-flips and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) increased system lifetime. However, selection of ECC scheme is dependent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) on various other factors also like;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) (1) support of built in hardware engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) Some legacy OMAP SoC do not have ELM harware engine, so those SoC cannot
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) support ecc-schemes with hardware error-correction (BCHx_HW). However
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) such SoC can use ecc-schemes with software library for error-correction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) (BCHx_HW_DETECTION_SW). The error correction capability with software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) library remains equivalent to their hardware counter-part, but there is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) slight CPU penalty when too many bit-flips are detected during reads.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) (2) Device parameters like OOBSIZE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) Other factor which governs the selection of ecc-scheme is oob-size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) Higher ECC schemes require more OOB/Spare area to store ECC syndrome,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) so the device should have enough free bytes available its OOB/Spare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) area to accommodate ECC for entire page. In general following expression
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) helps in determining if given device can accommodate ECC syndrome:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) "2 + (PAGESIZE / 512) * ECC_BYTES" <= OOBSIZE"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) where
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) OOBSIZE number of bytes in OOB/spare area
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PAGESIZE number of bytes in main-area of device page
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) ECC_BYTES number of ECC bytes generated to protect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 512 bytes of data, which is:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) '3' for HAM1_xx ecc schemes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) '7' for BCH4_xx ecc schemes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) '14' for BCH8_xx ecc schemes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) '26' for BCH16_xx ecc schemes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) Example(a): For a device with PAGESIZE = 2048 and OOBSIZE = 64 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) which is greater than capacity of NAND device (OOBSIZE=64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) Hence, BCH16 cannot be supported on given device. But it can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) probably use lower ecc-schemes like BCH8.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) Example(b): For a device with PAGESIZE = 2048 and OOBSIZE = 128 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) trying to use BCH16 (ECC_BYTES=26) ecc-scheme.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) Number of ECC bytes per page = (2 + (2048 / 512) * 26) = 106 B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) which can be accommodated in the OOB/Spare area of this device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) (OOBSIZE=128). So this device can use BCH16 ecc-scheme.
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Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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