Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) GPIO assisted NAND flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) The GPIO assisted NAND flash uses a memory mapped interface to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) read/write the NAND commands and data and GPIO pins for the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible : "gpio-control-nand"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - reg : should specify localbus chip select and size used for the chip.  The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   resource describes the data bus connected to the NAND flash and all accesses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   are made in native endianness.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - #address-cells, #size-cells : Must be present if the device has sub-nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   representing partitions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - gpios : Specifies the GPIO pins to control the NAND device.  The order of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   GPIO references is:  RDY, nCE, ALE, CLE, and nWP. nCE and nWP are optional.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - bank-width : Width (in bytes) of the device.  If not present, the width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   defaults to 1 byte.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - chip-delay : chip dependent delay for transferring data from array to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   read registers (tR).  If not present then a default of 20us is used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - gpio-control-nand,io-sync-reg : A 64-bit physical address for a read
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   location used to guard against bus reordering with regards to accesses to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   the GPIO's and the NAND flash data bus.  If present, then after changing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)   GPIO state and before and after command byte writes, this register will be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   read to ensure that the GPIO accesses have completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) The device tree may optionally contain sub-nodes describing partitions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) address space. See partition.txt for more detail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) gpio-nand@1,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	compatible = "gpio-control-nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	reg = <1 0x0000 0x2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	gpios = <&banka 1 0>,	/* RDY */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		<0>, 		/* nCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		<&banka 3 0>, 	/* ALE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		<&banka 4 0>, 	/* CLE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		<0>;		/* nWP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) };