Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) ST Microelectronics Flexible Static Memory Controller (FSMC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) NAND Interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - compatible : "st,spear600-fsmc-nand", "stericsson,fsmc-nand"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - reg : Address range of the mtd chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - reg-names: Should contain the reg names "fsmc_regs", "nand_data", "nand_addr" and "nand_cmd"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - bank-width : Width (in bytes) of the device.  If not present, the width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   defaults to 1 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - nand-skip-bbtscan: Indicates the BBT scanning should be skipped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - timings: array of 6 bytes for NAND timings. The meanings of these bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)   are:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   byte 0 TCLR  : CLE to RE delay in number of AHB clock cycles, only 4 bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)                  are valid. Zero means one clockcycle, 15 means 16 clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)                  cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   byte 1 TAR   : ALE to RE delay, 4 bits are valid. Same format as TCLR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   byte 2 THIZ  : number of HCLK clock cycles during which the data bus is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)                  kept in Hi-Z (tristate) after the start of a write access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)                  Only valid for write transactions. Zero means zero cycles,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)                  255 means 255 cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   byte 3 THOLD : number of HCLK clock cycles to hold the address (and data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)                  when writing) after the command deassertation. Zero means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)                  one cycle, 255 means 256 cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)   byte 4 TWAIT : number of HCLK clock cycles to assert the command to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)                  NAND flash in response to SMWAITn. Zero means 1 cycle,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)                  255 means 256 cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   byte 5 TSET  : number of HCLK clock cycles to assert the address before the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)                  command is asserted. Zero means one cycle, 255 means 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)                  cycles.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - bank: default NAND bank to use (0-3 are valid, 0 is the default).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - nand-ecc-mode      : see nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - nand-ecc-strength  : see nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - nand-ecc-step-size : see nand-controller.yaml
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) Can support 1-bit HW ECC (default) or if stronger correction is required,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) software-based BCH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	fsmc: flash@d1800000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		compatible = "st,spear600-fsmc-nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		reg = <0xd1800000 0x1000	/* FSMC Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		       0xd2000000 0x0010	/* NAND Base DATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		       0xd2020000 0x0010	/* NAND Base ADDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		       0xd2010000 0x0010>;	/* NAND Base CMD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		reg-names = "fsmc_regs", "nand_data", "nand_addr", "nand_cmd";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		bank-width = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		nand-skip-bbtscan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		timings = /bits/ 8 <0 0 0 2 3 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		bank = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 			...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 	};