Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) Freescale Localbus UPM programmed to work with NAND flash
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : "fsl,upm-nand".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg : should specify localbus chip select and size used for the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - fsl,upm-addr-offset : UPM pattern offset for the address latch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - fsl,upm-cmd-offset : UPM pattern offset for the command latch.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - fsl,upm-addr-line-cs-offsets : address offsets for multi-chip support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	The corresponding address lines are used to select the chip.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - gpios : may specify optional GPIOs connected to the Ready-Not-Busy pins
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	(R/B#). For multi-chip devices, "n" GPIO definitions are required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	according to the number of chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Deprecated properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - fsl,upm-wait-flags : add chip-dependent short delays after running the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 	UPM pattern (0x1), after writing a data byte (0x2) or after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	writing out a buffer (0x4).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - chip-delay : chip dependent delay for transferring data from array to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	read registers (tR). Required if property "gpios" is not used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	(R/B# pins not connected).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Each flash chip described may optionally contain additional sub-nodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) describing partitions of the address space. See partition.txt for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) detail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) upm@1,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	compatible = "fsl,upm-nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	reg = <1 0 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	fsl,upm-addr-offset = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	fsl,upm-cmd-offset = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 	gpios = <&qe_pio_e 18 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	flash {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		compatible = "...";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 			...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) upm@3,0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	#address-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	compatible = "tqc,tqm8548-upm-nand", "fsl,upm-nand";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	reg = <3 0x0 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 	fsl,upm-addr-offset = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	fsl,upm-cmd-offset = <0x08>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 	/* Multi-chip NAND device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 	fsl,upm-addr-line-cs-offsets = <0x0 0x200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 	nand@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		partition@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 			    label = "fs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			    reg = <0x00000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };