Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) FLCTL NAND controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : "renesas,shmobile-flctl-sh7372"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) - reg : Address range of the FLCTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) - interrupts : flste IRQ number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) - nand-bus-width : bus width to NAND chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - dmas: DMA specifier(s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - dma-names: name for each DMA specifier. Valid names are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 	     "data_tx", "data_rx", "ecc_tx", "ecc_rx"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) The DMA fields are not used yet in the driver but are listed here for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) completing the bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) The device tree may optionally contain sub-nodes describing partitions of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) address space. See partition.txt for more detail.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	flctl@e6a30000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 		compatible = "renesas,shmobile-flctl-sh7372";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 		reg = <0xe6a30000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 		interrupts = <0x0d80>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 		nand-bus-width = <16>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		dmas = <&dmac 1 /* data_tx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 			&dmac 2;> /* data_rx */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		dma-names = "data_tx", "data_rx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		system@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 			label = "system";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 			reg = <0x0 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		userdata@8000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 			label = "userdata";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 			reg = <0x8000000 0x10000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		cache@18000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 			label = "cache";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 			reg = <0x18000000 0x8000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	};