Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Cadence Quad SPI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) - compatible : should be one of the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 	Generic default - "cdns,qspi-nor".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	For TI 66AK2G SoC - "ti,k2g-qspi", "cdns,qspi-nor".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	For TI AM654 SoC  - "ti,am654-ospi", "cdns,qspi-nor".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - reg : Contains two entries, each of which is a tuple consisting of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 	physical address and length. The first entry is the address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 	length of the controller register set. The second entry is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 	address and length of the QSPI Controller data area.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts : Unit interrupt specifier for the controller interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks : phandle to the Quad SPI clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - cdns,fifo-depth : Size of the data FIFO in words.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - cdns,fifo-width : Bus width of the data FIFO in bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - cdns,trigger-address : 32-bit indirect AHB trigger address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - cdns,is-decoded-cs : Flag to indicate whether decoder is used or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - cdns,rclk-en : Flag to indicate that QSPI return clock is used to latch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   the read data rather than the QSPI clock. Make sure that QSPI return
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)   clock is populated on the board before using this property.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Optional subnodes:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) Subnodes of the Cadence Quad SPI controller are spi slave nodes with additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) custom properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - cdns,read-delay : Delay for read capture logic, in clock cycles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - cdns,tshsl-ns : Delay in nanoseconds for the length that the master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)                   mode chip select outputs are de-asserted between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		  transactions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - cdns,tsd2d-ns : Delay in nanoseconds between one chip select being
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)                   de-activated and the activation of another.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - cdns,tchsh-ns : Delay in nanoseconds between last bit of current
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)                   transaction and deasserting the device chip select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		  (qspi_n_ss_out).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - cdns,tslch-ns : Delay in nanoseconds between setting qspi_n_ss_out low
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)                   and first bit transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - resets	: Must contain an entry for each entry in reset-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		  See ../reset/reset.txt for details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - reset-names	: Must include either "qspi" and/or "qspi-ocp".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	qspi: spi@ff705000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		compatible = "cdns,qspi-nor";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		reg = <0xff705000 0x1000>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		      <0xffa00000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 		interrupts = <0 151 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 		clocks = <&qspi_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 		cdns,is-decoded-cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 		cdns,fifo-depth = <128>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 		cdns,fifo-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		cdns,trigger-address = <0x00000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		resets = <&rst QSPI_RESET>, <&rst QSPI_OCP_RESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		reset-names = "qspi", "qspi-ocp";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		flash0: n25q00@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 			...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 			cdns,read-delay = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 			cdns,tshsl-ns = <50>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 			cdns,tsd2d-ns = <50>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 			cdns,tchsh-ns = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 			cdns,tslch-ns = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 	};