Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Cadence NAND controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)   - compatible : "cdns,hp-nfc"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)   - reg : Contains two entries, each of which is a tuple consisting of a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 	  physical address and length. The first entry is the address and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 	  length of the controller register set. The second entry is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 	  address and length of the Slave DMA data port.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)   - reg-names: should contain "reg" and "sdma"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - #address-cells: should be 1. The cell encodes the chip select connection.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)   - #size-cells : should be 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   - interrupts : The interrupt number.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - clocks: phandle of the controller core clock (nf_clk).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   - dmas: shall reference DMA channel associated to the NAND controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   - cdns,board-delay-ps : Estimated Board delay. The value includes the total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)     round trip delay for the signals and is used for deciding on values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)     associated with data read capture. The example formula for SDR mode is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)     the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)     board delay = RE#PAD delay + PCB trace to device + PCB trace from device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)     + DQ PAD delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Child nodes represent the available NAND chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) Required properties of NAND chips:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)   - reg: shall contain the native Chip Select ids from 0 to max supported by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)     the cadence nand flash controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) See Documentation/devicetree/bindings/mtd/nand-controller.yaml for more details on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) generic bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) nand_controller: nand-controller@60000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 	  compatible = "cdns,hp-nfc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	  #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	  #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	  reg = <0x60000000 0x10000>, <0x80000000 0x10000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	  reg-names = "reg", "sdma";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	  clocks = <&nf_clk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	  cdns,board-delay-ps = <4830>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	  interrupts = <2 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 	  nand@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 	      reg = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 	      label = "nand-1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 	  };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 	  nand@1 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	      reg = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	      label = "nand-2";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 	  };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) };