Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Aspeed Firmware Memory controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) * Aspeed SPI Flash Memory Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) The Firmware Memory Controller in the Aspeed AST2500 SoC supports
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) three chip selects, two of which are always of SPI type and the third
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) can be SPI or NOR type flash. These bindings only describe SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) The two SPI flash memory controllers in the AST2500 each support two
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) chip selects.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)   - compatible : Should be one of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 	"aspeed,ast2400-fmc" for the AST2400 Firmware Memory Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 	"aspeed,ast2400-spi" for the AST2400 SPI Flash memory Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 	"aspeed,ast2500-fmc" for the AST2500 Firmware Memory Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	"aspeed,ast2500-spi" for the AST2500 SPI flash memory controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - reg : the first contains the control register location and length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)           the second contains the memory window mapping address and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   - #address-cells : must be 1 corresponding to chip select child binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   - #size-cells : must be 0 corresponding to chip select child binding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)   - interrupts : Should contain the interrupt for the dma device if an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)     FMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) The child nodes are the SPI flash modules which must have a compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) property as specified in bindings/mtd/jedec,spi-nor.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Optionally, the child node can contain properties for SPI mode (may be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) ignored):
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)   - spi-max-frequency - max frequency of spi bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) fmc: fmc@1e620000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	compatible = "aspeed,ast2500-fmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 	reg = < 0x1e620000 0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 		0x20000000 0x02000000 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 	#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 	interrupts = <19>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 	flash@0 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		reg = < 0 >;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		compatible = "jedec,spi-nor";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		/* spi-max-frequency = <>; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		/* m25p,fast-read; */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		#size-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };