^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Wondermedia WM8505/WM8650 SD/MMC Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This file documents differences between the core properties described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) by mmc.txt and the properties used by the wmt-sdmmc driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible: Should be "wm,wm8505-sdhc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - interrupts: Two interrupts are required - regular irq and dma irq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - sdon-inverted: SD_ON bit is inverted on the controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) sdhc@d800a000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) compatible = "wm,wm8505-sdhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) reg = <0xd800a000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) interrupts = <20 21>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) clocks = <&sdhc>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) sdon-inverted;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)