Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) $id: http://devicetree.org/schemas/mmc/synopsys-dw-mshc-common.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) $schema: http://devicetree.org/meta-schemas/core.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) title: Synopsys Designware Mobile Storage Host Controller Common Properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)   - $ref: "mmc-controller.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)   - Ulf Hansson <ulf.hansson@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) # Everything else is described in the common file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)   resets:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   reset-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)     const: reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)   clock-frequency:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)       Should be the frequency (in Hz) of the ciu clock.  If this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)       is specified and the ciu clock is specified then we'll try to set the ciu
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)       clock to this at probe time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)   fifo-depth:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)       The maximum size of the tx/rx fifo's. If this property is not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)       specified, the default value of the fifo size is determined from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)       controller registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)     $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)   card-detect-delay:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)       Delay in milli-seconds before detecting card after card
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)       insert event. The default value is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)     $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)     default: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)   data-addr:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)       Override fifo address with value provided by DT. The default FIFO reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)       offset is assumed as 0x100 (version < 0x240A) and 0x200(version >= 0x240A)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)       by driver. If the controller does not follow this rule, please use
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)       this property to set fifo address in device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)     $ref: /schemas/types.yaml#/definitions/uint32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)   fifo-watermark-aligned:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)     description:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)       Data done irq is expected if data length is less than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)       watermark in PIO mode. But fifo watermark is requested to be aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)       with data length in some SoC so that TX/RX irq can be generated with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)       data done irq. Add this watermark quirk to mark this requirement and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)       force fifo watermark setting accordingly.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)     $ref: /schemas/types.yaml#/definitions/flag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)   dmas:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)     maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)   dma-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)     const: rx-tx
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) additionalProperties: true