^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Altera SOCFPGA specific extensions to the Synopsys Designware Mobile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) Storage Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) The Synopsys designware mobile storage host controller is used to interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) differences between the core Synopsys dw mshc controller properties described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) by synopsys-dw-mshc.txt and the properties used by the Altera SOCFPGA specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) extensions to the Synopsys Designware Mobile Storage Host Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * compatible: should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - "altr,socfpga-dw-mshc": for Altera's SOCFPGA platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) mmc: dwmmc0@ff704000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) compatible = "altr,socfpga-dw-mshc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) reg = <0xff704000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) interrupts = <0 129 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };