^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * STMicroelectronics sdhci-st MMC/SD controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This file documents the differences between the core properties in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) Documentation/devicetree/bindings/mmc/mmc.txt and the properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) used by the sdhci-st driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) - compatible: Must be "st,sdhci" and it can be compatible to "st,sdhci-stih407"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) to set the internal glue logic used for configuring the MMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) subsystem (mmcss) inside the FlashSS (available in STiH407 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) family).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clock-names: Should be "mmc" and "icn". (NB: The latter is not compulsory)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) See: Documentation/devicetree/bindings/resource-names.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - clocks: Phandle to the clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) See: Documentation/devicetree/bindings/clock/clock-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - interrupts: One mmc interrupt should be described here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - interrupt-names: Should be "mmcirq".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - pinctrl-names: A pinctrl state names "default" must be defined.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - pinctrl-0: Phandle referencing pin configuration of the sd/emmc controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) See: Documentation/devicetree/bindings/pinctrl/pinctrl-bindings.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - reg: This must provide the host controller base address and it can also
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) contain the FlashSS Top register for TX/RX delay used by the driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) to configure DLL inside the flashSS, if so reg-names must also be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - reg-names: Should be "mmc" and "top-mmc-delay". "top-mmc-delay" is optional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) for eMMC on stih407 family silicon to configure DLL inside FlashSS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - non-removable: Non-removable slot. Also used for configuring mmcss in STiH407 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) family.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) See: Documentation/devicetree/bindings/mmc/mmc.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - bus-width: Number of data lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) See: Documentation/devicetree/bindings/mmc/mmc.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - max-frequency: Can be 200MHz, 100MHz or 50MHz (default) and used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) configuring the CCONFIG3 in the mmcss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) See: Documentation/devicetree/bindings/mmc/mmc.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) - resets: Phandle and reset specifier pair to softreset line of HC IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) See: Documentation/devicetree/bindings/reset/reset.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) - vqmmc-supply: Phandle to the regulator dt node, mentioned as the vcc/vdd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) supply in eMMC/SD specs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) - sd-uhs-sdr50: To enable the SDR50 in the mmcss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) See: Documentation/devicetree/bindings/mmc/mmc.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - sd-uhs-sdr104: To enable the SDR104 in the mmcss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) See: Documentation/devicetree/bindings/mmc/mmc.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - sd-uhs-ddr50: To enable the DDR50 in the mmcss.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) See: Documentation/devicetree/bindings/mmc/mmc.txt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Example stih416e eMMC configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) mmc0: sdhci@fe81e000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) compatible = "st,sdhci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) reg = <0xfe81e000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) interrupts = <GIC_SPI 127 IRQ_TYPE_NONE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) interrupt-names = "mmcirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) pinctrl-0 = <&pinctrl_mmc0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) clock-names = "mmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) clocks = <&clk_s_a1_ls 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) bus-width = <8>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Example SD stih407 family configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mmc1: sdhci@9080000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) compatible = "st,sdhci-stih407", "st,sdhci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = <0x09080000 0x7ff>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) reg-names = "mmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) interrupts = <GIC_SPI 90 IRQ_TYPE_NONE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) interrupt-names = "mmcirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) pinctrl-0 = <&pinctrl_sd1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) clock-names = "mmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) clocks = <&clk_s_c0_flexgen CLK_MMC_1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) resets = <&softreset STIH407_MMC1_SOFTRESET>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Example eMMC stih407 family configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) mmc0: sdhci@9060000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) compatible = "st,sdhci-stih407", "st,sdhci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) reg = <0x09060000 0x7ff>, <0x9061008 0x20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) reg-names = "mmc", "top-mmc-delay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) interrupts = <GIC_SPI 92 IRQ_TYPE_NONE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) interrupt-names = "mmcirq";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) pinctrl-0 = <&pinctrl_mmc0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) clock-names = "mmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) clocks = <&clk_s_c0_flexgen CLK_MMC_0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) vqmmc-supply = <&vmmc_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) max-frequency = <200000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bus-width = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) non-removable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) sd-uhs-sdr50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) sd-uhs-sdr104;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) sd-uhs-ddr50;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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