^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Spreadtrum SDHCI controller (sdhci-sprd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The Secure Digital (SD) Host controller on Spreadtrum SoCs provides an interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) for MMC, SD and SDIO types of cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) This file documents differences between the core properties in mmc.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) and the properties used by the sdhci-sprd driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible: Should contain "sprd,sdhci-r11".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - reg: physical base address of the controller and length.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - interrupts: Interrupts used by the SDHCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) - clocks: Should contain phandle for the clock feeding the SDHCI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - clock-names: Should contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "sdio" - SDIO source clock (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "enable" - gate clock which used for enabling/disabling the device (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "2x_enable" - gate clock controlling the device for some special platforms (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - assigned-clocks: the same with "sdio" clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - assigned-clock-parents: the default parent of "sdio" clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - pinctrl-names: should be "default", "state_uhs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - pinctrl-0: should contain default/high speed pin control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - pinctrl-1: should contain uhs mode pin control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) PHY DLL delays are used to delay the data valid window, and align the window
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) to sampling clock. PHY DLL delays can be configured by following properties,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) and each property contains 4 cells which are used to configure the clock data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) write line delay value, clock read command line delay value, clock read data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) positive edge delay value and clock read data negative edge delay value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) Each cell's delay value unit is cycle of the PHY clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - sprd,phy-delay-legacy: Delay value for legacy timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - sprd,phy-delay-sd-highspeed: Delay value for SD high-speed timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - sprd,phy-delay-sd-uhs-sdr50: Delay value for SD UHS SDR50 timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - sprd,phy-delay-sd-uhs-sdr104: Delay value for SD UHS SDR50 timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - sprd,phy-delay-mmc-highspeed: Delay value for MMC high-speed timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - sprd,phy-delay-mmc-ddr52: Delay value for MMC DDR52 timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - sprd,phy-delay-mmc-hs200: Delay value for MMC HS200 timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - sprd,phy-delay-mmc-hs400: Delay value for MMC HS400 timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - sprd,phy-delay-mmc-hs400es: Delay value for MMC HS400 enhanced strobe timing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) sdio0: sdio@20600000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) compatible = "sprd,sdhci-r11";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) reg = <0 0x20600000 0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) clock-names = "sdio", "enable";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) clocks = <&ap_clk CLK_EMMC_2X>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) <&apahb_gate CLK_EMMC_EB>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) assigned-clocks = <&ap_clk CLK_EMMC_2X>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) assigned-clock-parents = <&rpll CLK_RPLL_390M>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) pinctrl-names = "default", "state_uhs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) pinctrl-0 = <&sd0_pins_default>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) pinctrl-1 = <&sd0_pins_uhs>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) sprd,phy-delay-sd-uhs-sdr104 = <0x3f 0x7f 0x2e 0x2e>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) bus-width = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) non-removable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) no-sdio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) no-sd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) cap-mmc-hw-reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) status = "okay";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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