^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Qualcomm SDHCI controller (sdhci-msm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) This file documents differences between the core properties in mmc.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) and the properties used by the sdhci-msm driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) - compatible: Should contain a SoC-specific string and a IP version string:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) version strings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) "qcom,sdhci-msm-v4" for sdcc versions less than 5.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) "qcom,sdhci-msm-v5" for sdcc version 5.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) For SDCC version 5.0.0, MCI registers are removed from SDCC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) interface and some registers are moved to HC. New compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) string is added to support this change - "qcom,sdhci-msm-v5".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) full compatible strings with SoC and version:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "qcom,apq8084-sdhci", "qcom,sdhci-msm-v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "qcom,msm8916-sdhci", "qcom,sdhci-msm-v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "qcom,msm8992-sdhci", "qcom,sdhci-msm-v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "qcom,msm8996-sdhci", "qcom,sdhci-msm-v4"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "qcom,sm8250-sdhci", "qcom,sdhci-msm-v5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "qcom,sdm845-sdhci", "qcom,sdhci-msm-v5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "qcom,qcs404-sdhci", "qcom,sdhci-msm-v5"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "qcom,sc7180-sdhci", "qcom,sdhci-msm-v5";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) NOTE that some old device tree files may be floating around that only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) have the string "qcom,sdhci-msm-v4" without the SoC compatible string
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) but doing that should be considered a deprecated practice.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - reg: Base address and length of the register in the following order:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) - Host controller register map (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - SD Core register map (required for controllers earlier than msm-v5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - CQE register map (Optional, CQE support is present on SDHC instance meant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) for eMMC and version v4.2 and above)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - Inline Crypto Engine register map (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - reg-names: When CQE register map is supplied, below reg-names are required
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) - "hc" for Host controller register map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - "core" for SD core register map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - "cqhci" for CQE register map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - "ice" for Inline Crypto Engine register map (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - interrupts: Should contain an interrupt-specifiers for the interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - Host controller interrupt (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - pinctrl-names: Should contain only one value - "default".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - pinctrl-0: Should specify pin control groups used for this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - clocks: A list of phandle + clock-specifier pairs for the clocks listed in clock-names.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - clock-names: Should contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "iface" - Main peripheral bus clock (PCLK/HCLK - AHB Bus clock) (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "core" - SDC MMC clock (MCLK) (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "bus" - SDCC bus voter clock (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "xo" - TCXO clock (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "cal" - reference clock for RCLK delay calibration (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "sleep" - sleep clock for RCLK delay calibration (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) "ice" - clock for Inline Crypto Engine (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - qcom,ddr-config: Certain chipsets and platforms require particular settings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) for the DDR_CONFIG register. Use this field to specify the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) value as per the Hardware Programming Guide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) - qcom,dll-config: Chipset and Platform specific value. Use this field to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) specify the DLL_CONFIG register value as per Hardware Programming Guide.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) Optional Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * Following bus parameters are required for interconnect bandwidth scaling:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) - interconnects: Pairs of phandles and interconnect provider specifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) to denote the edge source and destination ports of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) the interconnect path.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) - interconnect-names: For sdhc, we have two main paths.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 1. Data path : sdhc to ddr
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 2. Config path : cpu to sdhc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) For Data interconnect path the name supposed to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) is "sdhc-ddr" and for config interconnect path it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "cpu-sdhc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Please refer to Documentation/devicetree/bindings/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) interconnect/ for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) sdhc_1: sdhci@f9824900 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) reg = <0xf9824900 0x11c>, <0xf9824000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) interrupts = <0 123 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) bus-width = <8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) non-removable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) vmmc-supply = <&pm8941_l20>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) vqmmc-supply = <&pm8941_s3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pinctrl-0 = <&sdc1_clk &sdc1_cmd &sdc1_data>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) clocks = <&gcc GCC_SDCC1_APPS_CLK>, <&gcc GCC_SDCC1_AHB_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clock-names = "core", "iface";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) interconnects = <&qnoc MASTER_SDCC_ID &qnoc SLAVE_DDR_ID>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) <&qnoc MASTER_CPU_ID &qnoc SLAVE_SDCC_ID>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) interconnect-names = "sdhc-ddr","cpu-sdhc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) qcom,dll-config = <0x000f642c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) qcom,ddr-config = <0x80040868>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) sdhc_2: sdhci@f98a4900 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) compatible = "qcom,msm8974-sdhci", "qcom,sdhci-msm-v4";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) reg = <0xf98a4900 0x11c>, <0xf98a4000 0x800>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) interrupts = <0 125 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) cd-gpios = <&msmgpio 62 0x1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) vmmc-supply = <&pm8941_l21>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) vqmmc-supply = <&pm8941_l13>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) pinctrl-0 = <&sdc2_clk &sdc2_cmd &sdc2_data>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) clocks = <&gcc GCC_SDCC2_APPS_CLK>, <&gcc GCC_SDCC2_AHB_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) clock-names = "core", "iface";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) qcom,dll-config = <0x0007642c>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) qcom,ddr-config = <0x80040868>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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