Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Atmel SDHCI controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) This file documents the differences between the core properties in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Documentation/devicetree/bindings/mmc/mmc.txt and the properties used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) sdhci-of-at91 driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) - compatible:		Must be "atmel,sama5d2-sdhci" or "microchip,sam9x60-sdhci".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) - clocks:		Phandlers to the clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - clock-names:		Must be "hclock", "multclk", "baseclk" for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 			"atmel,sama5d2-sdhci".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 			Must be "hclock", "multclk" for "microchip,sam9x60-sdhci".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) - assigned-clocks:	The same with "multclk".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - assigned-clock-rates	The rate of "multclk" in order to not rely on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 			gck configuration set by previous components.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - microchip,sdcal-inverted: when present, polarity on the SDCAL SoC pin is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   inverted. The default polarity for this signal is described in the datasheet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)   For instance on SAMA5D2, the pin is usually tied to the GND with a resistor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)   and a capacitor (see "SDMMC I/O Calibration" chapter).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) mmc0: sdio-host@a0000000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	compatible = "atmel,sama5d2-sdhci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 	reg = <0xa0000000 0x300>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	interrupts = <31 IRQ_TYPE_LEVEL_HIGH 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	clocks = <&sdmmc0_hclk>, <&sdmmc0_gclk>, <&main>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 	clock-names = "hclock", "multclk", "baseclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	assigned-clocks = <&sdmmc0_gclk>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	assigned-clock-rates = <480000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) };