^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) # Copyright (C) 2020 Texas Instruments Incorporated - http://www.ti.com/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) %YAML 1.2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) ---
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) $id: "http://devicetree.org/schemas/mmc/sdhci-am654.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) $schema: "http://devicetree.org/meta-schemas/core.yaml#"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) title: TI AM654 MMC Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) maintainers:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - Ulf Hansson <ulf.hansson@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) allOf:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) - $ref: mmc-controller.yaml#
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) compatible:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) - ti,am654-sdhci-5.1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - ti,j721e-sdhci-8bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) - ti,j721e-sdhci-4bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - ti,j7200-sdhci-8bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - ti,j721e-sdhci-4bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) interrupts:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) power-domains:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) maxItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) clocks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) description: Handles to input clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) clock-names:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) minItems: 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) maxItems: 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) items:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - const: clk_ahb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) - const: clk_xin
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) # PHY output tap delays:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) # Used to delay the data valid window and align it to the sampling clock.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) # Binding needs to be provided for each supported speed mode otherwise the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) # corresponding mode will be disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ti,otap-del-sel-legacy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) description: Output tap delay for SD/MMC legacy timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) ti,otap-del-sel-mmc-hs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) description: Output tap delay for MMC high speed timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) ti,otap-del-sel-sd-hs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) description: Output tap delay for SD high speed timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) ti,otap-del-sel-sdr12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) description: Output tap delay for SD UHS SDR12 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) ti,otap-del-sel-sdr25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) description: Output tap delay for SD UHS SDR25 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) ti,otap-del-sel-sdr50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) description: Output tap delay for SD UHS SDR50 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) ti,otap-del-sel-sdr104:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) description: Output tap delay for SD UHS SDR104 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) ti,otap-del-sel-ddr50:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) description: Output tap delay for SD UHS DDR50 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) ti,otap-del-sel-ddr52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) description: Output tap delay for eMMC DDR52 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) ti,otap-del-sel-hs200:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) description: Output tap delay for eMMC HS200 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) ti,otap-del-sel-hs400:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) description: Output tap delay for eMMC HS400 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) # PHY input tap delays:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) # Used to delay the data valid window and align it to the sampling clock for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) # modes that don't support tuning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) ti,itap-del-sel-legacy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) description: Input tap delay for SD/MMC legacy timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) maximum: 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) ti,itap-del-sel-mmc-hs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) description: Input tap delay for MMC high speed timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) maximum: 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) ti,itap-del-sel-sd-hs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) description: Input tap delay for SD high speed timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) maximum: 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) ti,itap-del-sel-sdr12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) description: Input tap delay for SD UHS SDR12 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) maximum: 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) ti,itap-del-sel-sdr25:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) description: Input tap delay for SD UHS SDR25 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) maximum: 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) ti,itap-del-sel-ddr52:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) description: Input tap delay for MMC DDR52 timing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) maximum: 0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ti,trm-icp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) description: DLL trim select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) minimum: 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) maximum: 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ti,driver-strength-ohm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) description: DLL drive strength in ohms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) - 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) - 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) - 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) - 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) - 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ti,strobe-sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) description: strobe select delay for HS400 speed mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) ti,clkbuf-sel:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) description: Clock Delay Buffer Select
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) $ref: "/schemas/types.yaml#/definitions/uint32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) required:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) - compatible
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) - reg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) - interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) - clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) - clock-names
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) - ti,otap-del-sel-legacy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unevaluatedProperties: false
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) - |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #include <dt-bindings/interrupt-controller/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #include <dt-bindings/interrupt-controller/arm-gic.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #address-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #size-cells = <2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) mmc0: mmc@4f80000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) compatible = "ti,am654-sdhci-5.1";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) power-domains = <&k3_pds 47>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) clocks = <&k3_clks 47 0>, <&k3_clks 47 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) clock-names = "clk_ahb", "clk_xin";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) sdhci-caps-mask = <0x80000007 0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) mmc-ddr-1_8v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ti,otap-del-sel-legacy = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) ti,otap-del-sel-mmc-hs = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) ti,otap-del-sel-ddr52 = <0x5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) ti,otap-del-sel-hs200 = <0x5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ti,otap-del-sel-hs400 = <0x0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) ti,itap-del-sel-legacy = <0x10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) ti,itap-del-sel-mmc-hs = <0xa>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ti,itap-del-sel-ddr52 = <0x3>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) ti,trm-icp = <0x8>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags