^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * Samsung's SDHCI Controller device tree bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) Samsung's SDHCI controller is used as a connectivity interface with external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) MMC, SD and eMMC storage mediums. This file documents differences between the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) core mmc properties described by mmc.txt and the properties used by the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) Samsung implementation of the SDHCI controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) Required SoC Specific Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) - compatible: should be one of the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - "samsung,s3c6410-sdhci": For controllers compatible with s3c6410 sdhci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - "samsung,exynos4210-sdhci": For controllers compatible with Exynos4 sdhci
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Required Board Specific Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - pinctrl-0: Should specify pin control groups used for this controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) - pinctrl-names: Should contain only one value - "default".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) sdhci@12530000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) compatible = "samsung,exynos4210-sdhci";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) reg = <0x12530000 0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) interrupts = <0 75 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) cd-gpios = <&gpk2 2 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) pinctrl-0 = <&sd0_clk &sd0_cmd &sd0_bus4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) Note: This example shows both SoC specific and board specific properties
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) in a single device node. The properties can be actually be separated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) into SoC specific node and board specific node.