^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * MTK MMC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The MTK MSDC can act as a MMC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) to support MMC, SD, and SDIO types of memory cards.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) This file documents differences between the core properties in mmc.txt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) and the properties used by the msdc driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) - compatible: value should be either of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "mediatek,mt8135-mmc": for mmc host ip compatible with mt8135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "mediatek,mt8173-mmc": for mmc host ip compatible with mt8173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "mediatek,mt8183-mmc": for mmc host ip compatible with mt8183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "mediatek,mt8516-mmc": for mmc host ip compatible with mt8516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "mediatek,mt6779-mmc": for mmc host ip compatible with mt6779
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "mediatek,mt2701-mmc": for mmc host ip compatible with mt2701
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "mediatek,mt2712-mmc": for mmc host ip compatible with mt2712
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "mediatek,mt7622-mmc": for MT7622 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) "mediatek,mt7623-mmc", "mediatek,mt2701-mmc": for MT7623 SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "mediatek,mt7620-mmc", for MT7621 SoC (and others)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - reg: physical base address of the controller and length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - interrupts: Should contain MSDC interrupt number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - clocks: Should contain phandle for the clock feeding the MMC controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - clock-names: Should contain the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) "source" - source clock (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "hclk" - HCLK which used for host (required)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "source_cg" - independent source clock gate (required for MT2712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "bus_clk" - bus clock used for internal register access (required for MT2712 MSDC0/3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) - pinctrl-names: should be "default", "state_uhs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - pinctrl-0: should contain default/high speed pin ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) - pinctrl-1: should contain uhs mode pin ctrl
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - vmmc-supply: power to the Core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - vqmmc-supply: power to the IO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) - assigned-clocks: PLL of the source clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) - assigned-clock-parents: parent of source clock, used for HS400 mode to get 400Mhz source clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) - hs400-ds-delay: HS400 DS delay setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) - mediatek,hs200-cmd-int-delay: HS200 command internal delay setting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) This field has total 32 stages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) The value is an integer from 0 to 31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) - mediatek,hs400-cmd-int-delay: HS400 command internal delay setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) This field has total 32 stages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) The value is an integer from 0 to 31.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) - mediatek,hs400-cmd-resp-sel-rising: HS400 command response sample selection
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) If present,HS400 command responses are sampled on rising edges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) If not present,HS400 command responses are sampled on falling edges.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) - mediatek,latch-ck: Some SoCs do not support enhance_rx, need set correct latch-ck to avoid data crc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) error caused by stop clock(fifo full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) Valid range = [0:0x7]. if not present, default value is 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) applied to compatible "mediatek,mt2701-mmc".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) - resets: Phandle and reset specifier pair to softreset line of MSDC IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) - reset-names: Should be "hrst".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) Examples:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) mmc0: mmc@11230000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) compatible = "mediatek,mt8173-mmc", "mediatek,mt8135-mmc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) reg = <0 0x11230000 0 0x108>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_LOW>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) vmmc-supply = <&mt6397_vemc_3v3_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) vqmmc-supply = <&mt6397_vio18_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) clocks = <&pericfg CLK_PERI_MSDC30_0>,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) <&topckgen CLK_TOP_MSDC50_0_H_SEL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) clock-names = "source", "hclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) pinctrl-names = "default", "state_uhs";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pinctrl-0 = <&mmc0_pins_default>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) pinctrl-1 = <&mmc0_pins_uhs>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) assigned-clocks = <&topckgen CLK_TOP_MSDC50_0_SEL>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) hs400-ds-delay = <0x14015>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) mediatek,hs200-cmd-int-delay = <26>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) mediatek,hs400-cmd-int-delay = <14>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) mediatek,hs400-cmd-resp-sel-rising;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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