^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) * ARM PrimeCell MultiMedia Card Interface (MMCI) PL180/1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) The ARM PrimeCell MMCI PL180 and PL181 provides an interface for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) reading and writing to MultiMedia and SD cards alike.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) This file documents differences between the core properties described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) by mmc.txt and the properties used by the mmci driver. Using "st" as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) the prefix for a property, indicates support by the ST Micro variant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) Required properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) - compatible : contains "arm,pl18x", "arm,primecell".
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) - vmmc-supply : phandle to the regulator device tree node, mentioned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) as the VCC/VDD supply in the eMMC/SD specs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) Optional properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) - arm,primecell-periphid : contains the PrimeCell Peripheral ID, it overrides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) the ID provided by the HW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) - resets : phandle to internal reset line.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) Should be defined for sdmmc variant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) - vqmmc-supply : phandle to the regulator device tree node, mentioned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) as the VCCQ/VDD_IO supply in the eMMC/SD specs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) specific for ux500 variant:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) - st,sig-dir-dat0 : bus signal direction pin used for DAT[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) - st,sig-dir-dat2 : bus signal direction pin used for DAT[2].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) - st,sig-dir-dat31 : bus signal direction pin used for DAT[3] and DAT[1].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) - st,sig-dir-dat74 : bus signal direction pin used for DAT[4] to DAT[7].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) - st,sig-dir-cmd : cmd signal direction pin used for CMD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) - st,sig-pin-fbclk : feedback clock signal pin used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) specific for sdmmc variant:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) - reg : a second base register may be defined if a delay
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) block is present and used for tuning.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) - st,sig-dir : signal direction polarity used for cmd, dat0 dat123.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) - st,neg-edge : data & command phase relation, generated on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) sd clock falling edge.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) - st,use-ckin : use ckin pin from an external driver to sample
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) the receive data (example: with voltage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) switch transceiver).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Deprecated properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) - mmc-cap-mmc-highspeed : indicates whether MMC is high speed capable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) - mmc-cap-sd-highspeed : indicates whether SD is high speed capable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) sdi0_per1@80126000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) compatible = "arm,pl18x", "arm,primecell";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) reg = <0x80126000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) interrupts = <0 60 IRQ_TYPE_LEVEL_HIGH>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) dmas = <&dma 29 0 0x2>, /* Logical - DevToMem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) <&dma 29 0 0x0>; /* Logical - MemToDev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) dma-names = "rx", "tx";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) clocks = <&prcc_kclk 1 5>, <&prcc_pclk 1 5>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) clock-names = "sdi", "apb_pclk";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) max-frequency = <100000000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) cap-sd-highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) cap-mmc-highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) cd-gpios = <&gpio2 31 0x4>; // 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) st,sig-dir-dat0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) st,sig-dir-dat2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) st,sig-dir-cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) st,sig-pin-fbclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) vmmc-supply = <&ab8500_ldo_aux3_reg>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) vqmmc-supply = <&vmmci>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) pinctrl-names = "default", "sleep";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) pinctrl-0 = <&sdi0_default_mode>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) pinctrl-1 = <&sdi0_sleep_mode>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) };
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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