Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) * Hisilicon specific extensions to the Synopsys Designware Mobile
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)   Storage Host Controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) Read synopsys-dw-mshc.txt for more details
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) The Synopsys designware mobile storage host controller is used to interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) a SoC with storage medium such as eMMC or SD/MMC cards. This file documents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) differences between the core Synopsys dw mshc controller properties described
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) by synopsys-dw-mshc.txt and the properties used by the Hisilicon specific
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) extensions to the Synopsys Designware Mobile Storage Host Controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Required Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * compatible: should be one of the following.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)   - "hisilicon,hi3660-dw-mshc": for controllers with hi3660 specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)   - "hisilicon,hi3670-dw-mshc", "hisilicon,hi3660-dw-mshc": for controllers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)      with hi3670 specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)   - "hisilicon,hi4511-dw-mshc": for controllers with hi4511 specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)   - "hisilicon,hi6220-dw-mshc": for controllers with hi6220 specific extensions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) Optional Properties:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) - hisilicon,peripheral-syscon: phandle of syscon used to control peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) Example:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 	/* for Hi3620 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 	/* SoC portion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 	dwmmc_0: dwmmc0@fcd03000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 		compatible = "hisilicon,hi4511-dw-mshc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 		reg = <0xfcd03000 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 		interrupts = <0 16 4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 		#address-cells = <1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 		#size-cells = <0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 		clocks = <&mmc_clock HI3620_SD_CIUCLK>, <&clock HI3620_DDRC_PER_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 		clock-names = "ciu", "biu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 	/* Board portion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 	dwmmc0@fcd03000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		vmmc-supply = <&ldo12>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 		fifo-depth = <0x100>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 		pinctrl-names = "default";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) 		pinctrl-0 = <&sd_pmx_pins &sd_cfg_func1 &sd_cfg_func2>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 		bus-width = <4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		disable-wp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 		cd-gpios = <&gpio10 3 0>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 		cap-mmc-highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 		cap-sd-highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) 	/* for Hi6220 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 	dwmmc_1: dwmmc1@f723e000 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 		compatible = "hisilicon,hi6220-dw-mshc";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 		bus-width = <0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 		disable-wp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) 		cap-sd-highspeed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 		sd-uhs-sdr12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 		sd-uhs-sdr25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 		card-detect-delay = <200>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 		hisilicon,peripheral-syscon = <&ao_ctrl>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) 		reg = <0x0 0xf723e000 0x0 0x1000>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 		interrupts = <0x0 0x49 0x4>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) 		clocks = <&clock_sys HI6220_MMC1_CIUCLK>, <&clock_sys HI6220_MMC1_CLK>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 		clock-names = "ciu", "biu";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) 		cd-gpios = <&gpio1 0 1>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) 		pinctrl-names = "default", "idle";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 		pinctrl-0 = <&sd_pmx_func &sd_clk_cfg_func &sd_cfg_func>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) 		pinctrl-1 = <&sd_pmx_idle &sd_clk_cfg_idle &sd_cfg_idle>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) 		vqmmc-supply = <&ldo7>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) 		vmmc-supply = <&ldo10>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 	};